Principal Implementation Engineer - Power Intent Microarchitecture Lead at Arm
Sheffield S2 1EY, , United Kingdom -
Full Time


Start Date

Immediate

Expiry Date

11 Jun, 25

Salary

0.0

Posted On

12 Mar, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Computer Science, Clock Tree Synthesis, Upf, Synthesis, Power Delivery, Architecture, Tcl, Linux

Industry

Information Technology/IT

Description

We are bringing together excellent talent and expertise from across the semiconductor industry to drive how the next generation of leading AI compute on Arm devices are built. Thus opening up significant and exciting future potential!
Arm is rapidly growing the Central Engineering Systems team to develop best in class solutions based on Arm’s IP, addressing AI challenges in secure compute, large screen compute, infrastructure and automotive markets. We offer the outstanding opportunity for an experienced implementation engineer to join as a principal implementation engineer with expert knowledge in UPF power intent microarchitecture. You’ll be leading the initiative in driving Arm solutions development to optimize the power and performance. You will innovate, evolve and deliver optimal tape-out quality implementations.

REQUIRED SKILLS AND EXPERIENCE:

  • Writing and validating UPF
  • Experience with low power design techniques - clock and power gating, voltage/frequency scaling, retention
  • Algorithmic thinking, with some programming experience in Tcl, Make and Linux shell
  • The ability to analyse problems, reason logically about solutions and chart the appropriate course to take
  • Team work with good communication able to present ideas, results and conclusions in a proficient and organised way

’NICE TO HAVE’ SKILLS AND EXPERIENCE:

  • Knowledge of sophisticated low power techniques, control of power delivery LDO and external regulators & use on chip instrumentation.
  • Knowledge of systems architecture, Arm IP and Arm-based SoCs
  • A curiosity about AI hardware technology
  • Good understanding of the concepts related to Synthesis, Place & Route, Clock tree synthesis, constraint development, timing closure and knowledge of hardware languages: Verilog/System Verilog
  • Understanding of power delivery and experience of static and dynamic IR-drop analysis
  • Power and physical architecture
  • A curiosity about embracing new silicon implementation techniques and methodologies
  • A STEM degree in a relevant field, such as electronics engineering or computer science
Responsibilities
  • Leading the power intent for high performing complex implementations.
  • Work collaboratively with design teams influencing system micro architecture to achieve the highest standards.
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