Principal IO Design Architect, HBM at Micron Technology

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

20 Mar, 26

Salary

0.0

Posted On

20 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

High-Speed Clocking Design, IO Circuit Design, Analog Design, Digital Design, Circuit Verification, Layout Verification, Parasitic Extractions, Off-Chip Protocols, FinFET Device Characteristics, Problem-Solving, Analytical Skills, Communication Skills, Device Physics, CMOS Processing Techniques, Circuit Debug Experience, RTL Debugging

Industry

Semiconductor Manufacturing

Description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications! Our ultimate goal is to deliver the lowest power per bit solutions in the industry! Position Overview: We are searching for a Principal HBM IO Architecture Design engineer own the development of the PHY IO on the interface die in HBM products. In this position, you will be responsible for the development including defining design target, developing spec, architecting IO/clocking/datapath, being responsible for design, optimization, and verification. Use of both analog and digital CMOS design skills will be needed to work on the various circuits you would be responsible for. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful. Responsibilities will include, but are not limited to: IO and datapath design architect for HBM products Design low-power high-speed Tx, Rx, clock tree Analyze timing jitter and variation to improve speed and optimize design Contribute to cross group communication to work towards standardization and group success Proactively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality Drive innovation into the future Memory generation with multifaceted work environment Successful candidates for this position will have: Prior industrial experience in high-speed clocking design at 16Gbps+ speed Good IO circuit design background with familiarity of both, analog and digital design and simulation experience required Solid knowledge of IO design principles for practical design tradeoffs on speed/area/power/complexity Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits Familiar with one or more off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc Good understanding on FinFET device characteristics and hands-on design experience Excellent problem-solving and analytical skills Strong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers both verbally and written Understanding of device physics and basic CMOS processing techniques preferred Prior circuit debug experience through Product Engineering or equivalent preferred D2D design experience is a plus Familiar with IP level verification and strong RTL debugging capabilities is a plus Required Experience: Minimum 5+ years of proven experience in the Memory industry with an MS EE degree, or 7+ years with a BS EE or equivalent experience. Job title and level can scale depending on experience and qualifications About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Responsibilities

The Principal HBM IO Architecture Design engineer will develop the PHY IO on the interface die in HBM products, including defining design targets and optimizing designs. Responsibilities also include collaborating with a multi-functional team to ensure the success of the HBM roadmap.