Principal Layout Engineer, DPG at Micron Technology

Boise, Idaho, United States -

Full Time

Start Date

Immediate

Expiry Date

06 Jan, 26

Salary

0.0

Posted On

08 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Layout Design, Verification, Automation, Project Management, Mentoring, Collaboration, Scripting, CMOS Processes, DRC, LVS, Cadence Virtuoso, Calibre, Problem Solving, Quality Assurance, Documentation, Memory Product Layout

Industry

Semiconductor Manufacturing

Description

Design and Development: Create layout designs for critical circuits, ensuring compliance with process rules and schematic intent. Work closely with Design, Process, and CAD engineers to deliver solutions from floorplan through final design. Layout Verification: Perform verification tasks such as LVS (Layout vs. Schematic), DRC (Design Rule Check), and quality checks. Continuously improve verification tools and methodologies to ensure high‑quality layouts. Methods, Automation & Documentation: Tackle ambiguous problems; prototype solutions without a playbook; then codify them into guides/SOPs and share with the team. Contribute scripts (e.g., SKILL/Python) and layout method improvements to advance automation and drive measurable productivity gains. Integrate automated layout solutions to shape the future of layout design. On‑Time Delivery: Coordinate with global partners to meet predictable schedules and support tapeout/mask generation processes. Deliver block‑level layouts within specified timelines while maintaining quality standards. Project Management: Lead layout planning for assigned blocks or sub‑projects; coordinate priorities, provide guidance to other engineers, and ensure schedule alignment. Mentor team members on layout techniques, verification best practices, and tool usage. Bachelor's in Electrical/Computer Engineering (or related). Proficiency in layout tools and methodologies, including Cadence Virtuoso VXL and Calibre for DRC/LVS/Verifications. 2+ years of semiconductor custom/memory/analog layout experience. Solid understanding of CMOS processes, design rules, and layout‑dependent effects. Proven problem‑solving in ambiguity with high attention to detail and quality. 8+ years of semiconductor custom/memory/analog layout experience with demonstrated block/project leadership, including mentoring and schedule management. DRAM/LPDDR/HBM memory product layout background; familiarity with tapeout/mask generation flows. Scripting (SKILL, Python) and experience building methodology/automation. Strong collaboration skills across global, cross‑functional teams; excellent written documentation abilities.

Responsibilities

The Principal Layout Engineer will create layout designs for critical circuits and perform verification tasks to ensure high-quality layouts. They will also lead layout planning for assigned blocks, mentor team members, and integrate automated layout solutions.