Principal Static Timing Analysis Engineer at Microsoft

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

26 Mar, 26

Salary

0.0

Posted On

26 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, Circuit Design, Spice Modeling, Aging Simulations, Yield Analysis, EDA Tools, Noise Glitch Analysis, Interconnect Extraction, Timing Constraints Management, Automation Skills, Data Analysis, Problem Solving, Design Tradeoffs, Floorplan Optimization, Collaboration, Communication

Industry

Software Development

Description

Overview Microsoft's hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, business and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling, and DevOps supporting the development of custom silicon. Microsoft’s hardware teams are also expanding into new technologies such as quantum computing! We are looking for passionate professionals who will help us designing for the future! Responsibilities The silicon computing development team is seeking passionate, driven and intellectually curious engineers to join the back-end SoC design team covering static timing analysis (STA) methodology, design convergence and design quality for our projects. This new team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. In this high impact role on the team, you will: Drive IP and full-chip level timing closure for various SoC projects. Drive solutions for critical timing paths by collaborating with back-end, logic, floorplan and other relevant owners. Ensure quality by setting up a robust design signoff methodology covering areas such as variation, yield analysis, transistor aging, interconnect extraction, and noise analysis. Contribute to full-chip level timing model build, flow maintenance and release process. Manage timing constraint such as clock definitions, exceptions, block level IO constraints. Improve design execution efficiency through flow automation and indicator generation. Influence STA tools, flows, signoff accuracy and modeling efficiency with a data driven approach by engaging in various advanced EDA feature pioneering. Make good independent technical trade-offs between power, area, and timing. Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset. Apply your growth mindset to learn and adapt in a complex and dynamic environment. Qualifications Requirements: Candidate must have at least a bachelor’s degree in Electrical Engineering, Computer Engineering, or a related degree or equivalent work experience. Strong circuit design background with understanding in variation, spice modeling, aging simulations, yield analysis. Solid experience with EDA tools such Static Timing Analysis, Noise Glitch analysis, interconnect extraction. Understanding in managing timing constraints, exceptions, IP constraint promotion, efficient constraints practices etc. Excellent communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Preferred Additional Requirements: Strong problem-solving and data analysis skills Strong automation skills using scripting languages such as Perl, TCL, Python. In-depth understanding of design tradeoffs for power, performance, and area. Experience and knowledge of formal equivalency checks, LP, UPF, and reliability. Experience in floorplan optimization taking design convergence, power domain crossing and die area into account. This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Responsibilities

The role involves driving IP and full-chip level timing closure for various SoC projects and ensuring quality through a robust design signoff methodology. The engineer will also collaborate across teams to influence STA tools and improve design execution efficiency.