Principal Static Timing Analysis (STA) Engineer – SoC Design at Marvell Technology

Westborough, Massachusetts, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Jun, 26

Salary

0.0

Posted On

22 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, STA, SoC Design, Timing Closure, Physical Design, DFT, EDA Tools, PPA Goals, Timing Correlation, ECOs, Perl, Python, TCL, Timing Constraints, Synopsys PrimeTime, UNIX

Industry

Semiconductor Manufacturing

Description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The DCE team at Marvell is seeking a Principal Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wireless infrastructure—using the latest technology nodes. Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), and other cross-functional teams across both local and global sites. If you're looking to apply your STA expertise in a dynamic and forward-thinking environment, this could be a great opportunity to explore. What You Can Expect Lead timing closure for sub-system/partition or full-chip level designs Collaborate with RTL, DFT, and IP teams to drive iterative timing feedback and closure Deliver timing collateral and signoff reports per project milestones Perform timing correlation between PD tools and signoff tools; support early feasibility studies Generate and push down ECOs to block-level teams Mentor junior engineers and provide technical leadership across teams Develop automation scripts in Perl, Python, and TCL to improve timing workflows Manage timing constraints compatible with synthesis, P&R, and STA tools What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree Proven success in timing analysis and closure across multiple ASICs/SoCs Experience with advanced timing concepts: SI, CDC, LVF, POCV, etc. Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX environments Strong communication skills and ability to work independently and collaboratively Experience leading timing closure efforts across teams preferred Familiarity with timing methodology and flow development preferred Expected Base Pay Range (USD) 0 - 0, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-VM1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Responsibilities

The role involves leading timing closure for sub-system or full-chip designs, collaborating with RTL, DFT, and IP teams to drive iterative timing feedback, and delivering necessary timing collateral and signoff reports.