Principal Validation Engineer at Astera Labs

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

23 Apr, 26

Salary

230000.0

Posted On

23 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Mixed-Signal Systems, Validation, Characterization, Debugging, Test Methodologies, Python, C/C++, Signal Integrity, High-Speed Design, Protocol Analyzers, Performance Optimization, Root-Cause Analysis, Firmware Stability, NRZ/PAM4 Architectures, Post-Silicon Validation, Test Automation

Industry

Semiconductor Manufacturing

Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Overview: As a Principal Validation Engineer, you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets. You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction. This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production. You will: Be responsible for designing, developing, executing characterization and validation plan Participate in design reviews, design specifications and architecture Perform task including test execution, automation, debugging, silicon bringup, interop, performance optimization collaborate with cross-functional mixed signal design team to provide detailed results, RCA on issues, optimization, characterization, validation and compliance report. Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions. Collaborate with design, validation, and system engineering teams as needed. Document debug findings, propose design/process/test improvements, and contribute to FA methodologies. Develop python test scripts to configure, control, and get status from multiple DSP HW platforms for improving firmware stability. Basic Qualifications: Minimum of a Bachelor’s in Electrical Engineering while a Master’s degree is preferred. Minimum of 10 years relevant experience on hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA. Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing). Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity. Experience in post-silicon validation and bring-up of high-speed PHYs or retimers. Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures. Strong written and verbal communication skills. Preferred Experience: Experience in mixed-signal system testing, characterization, validation and compliance Hands-on experience with signal integrity test equipment and techniques Familiarity with IEEE 802.3x Ethernet standards Strong Python and C/C++ skills Working knowledge of common serial data specifications such as I2C, I3C, SPI, etc The base salary range is USD 185,00 - USD 230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Responsibilities

As a Principal Validation Engineer, you will lead the end-to-end post-silicon validation and characterization effort, owning the development and execution of comprehensive validation plans. You will collaborate with design, firmware, and system teams to translate architectural goals into measurable test strategies and analyze complex analog and digital interactions.