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R&D Engineering at Synopsys Inc

berlin, Berlin, Germany -

Full Time

Start Date

Immediate

Expiry Date

15 Jan, 27

Salary

50000.0

Posted On

17 Oct, 26

Experience

1 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Industry

Electrical Equipment Manufacturing

Description

Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD).
Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
Developing standalone test benches to verify the RTL behavior.
Writing and verifying SystemVerilog Assertions (SVA) for a design.
Writing timing constraints and clock definition for synthesis and place and route tools.
Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise.
Understanding various design tradeoffs including timing/area/power and knowing how to improve them.
Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time).
Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams.
Post-Si bring-up, validation, and debugging.

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Responsibilities