Overview:
Keysight is on the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.
Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.
Responsibilities:
Keysight Technologies has an exciting job opportunity for an ASIC DFT/Test Engineer. This position involves developing and testing leading edge ASICs, including some of the world’s fastest DACs and ADCs, that make it possible for Keysight to create and deliver new measurement products. This position is based in Colorado Springs, Colorado, which is ranked as one of the most desirable place to live by U.S. News & World Report.

JOB INTRODUCTION:

We are seeking a highly motivated ASIC Test Engineer / DFT (Design-For-Test) Engineer to join our team. As an ASIC Test Engineer, you will be responsible for designing and implementing testability features within Keysight ASICs, developing and executing test plans, designing test circuits, and performing electrical testing on our advanced ASIC designs to ensure quality and functionality.
Your background in electrical engineering, combined with your strong problem-solving and analytical skills, will contribute to the success of our cutting-edge ASICs.

Qualifications:

• Bachelor’s degree in Electrical Engineering or related field (minimum requirement)
• 1-3+ years of experience in ASIC testing or related roles (recent graduates or current college students graduating by December 2025 will be considered with applicable skills)
• Knowledge of ATE (Automatic Test Equipment) systems and hardware (strongly preferred)
• Strong understanding of digital and analog circuitry
• Experience in developing and debugging test programs on LINUX systems using industry-standard languages (e.g., C++, Verilog, VHDL, or similar development environment)
• Familiarity with lab equipment such as oscilloscopes, logic analyzers, and power supplies
• Strong analytical skills to decode test data and troubleshoot issues
• Aptitude for puzzles, challenges, and problem-solving
• Ability to effectively work in a team and independentl

• Test Methodology and Strategy: Developing test methodologies and strategies for validating the ASIC. This involves analyzing chip specifications, understanding functional requirements, and designing appropriate test techniques and methodologies to ensure comprehensive coverage of the chip’s functionality.
• Hardware Development: Developing hardware for package and wafer test systems, utilizing the Advantest 93K test platform; Create schematic captures of PCB boards and working with vendors throughout the layout and fabrication process.
• Design for Test (DFT): Collaborating with ASIC design engineers to incorporate testability features into the chip design. This includes integrating test structures and circuits that facilitate efficient testing and debugging, such as scan chains, boundary scan (JTAG) logic, built-in self-test (BIST) modules, and test access mechanisms.
• Test Program Development: Writing test programs or scripts for characterization and production testing.
• Test Execution and Debugging: Executing the developed test programs on the ASIC chips and analyzing the test results. The engineer identifies and isolates any failures or issues, working closely with design engineers to debug and resolve problems.
• Test Coverage Analysis: Assessing the effectiveness and coverage of the developed test strategies and patterns, evaluating the quality and thoroughness of the testing process and identifies any gaps or areas of improvement in test coverage.
• Fault Diagnosis and Failure Analysis: Investigating and diagnosing failures or defects found during testing. The engineer utilizes various diagnostic techniques and tools to analyze the root causes of failures and provides recommendations for corrective actions.
• Design Verification Support: Assisting in the verification of the ASIC chip design by developing and executing specific test cases or simulations to validate the functionality and performance of the design.
• Collaboration and Communication: Collaborating with cross-functional teams, including design engineers, product managers, and test managers, to ensure effective communication and coordination throughout the testing and development lifecycle. You will participate in design reviews, test strategy discussions, and project meetings to align testing efforts with project goals.

Qualifications:

• Bachelor’s degree in Electrical Engineering or related field (minimum requirement)
• 1-3+ years of experience in ASIC testing or related roles (recent graduates or current college students graduating by December 2025 will be considered with applicable skills)
• Knowledge of ATE (Automatic Test Equipment) systems and hardware (strongly preferred)
• Strong understanding of digital and analog circuitry
• Experience in developing and debugging test programs on LINUX systems using industry-standard languages (e.g., C++, Verilog, VHDL, or similar development environment)
• Familiarity with lab equipment such as oscilloscopes, logic analyzers, and power supplies
• Strong analytical skills to decode test data and troubleshoot issues
• Aptitude for puzzles, challenges, and problem-solving
• Ability to effectively work in a team and independently

Preferred candidates will have:

• Experience with Advantest 93K ATE Tester
• Experience with ASIC design verification methodologies and tools (e.g., UVM, SystemVerilog)
• Familiarity with ASIC design and test methodologies
• Experience with DFT tools such as Tessen