BACKGROUND TO THE ROLE

Within Tyndall’s Micro Nano Systems Centre, we have created a strategic research programme focusing on materials, emerging devices and architectures for future information processing, interfacing with CMOS and beyond (“CMOS++ Materials & Devices”).
CMOS++ is involved in the Chips JU NanoIC pilot line co-funded by the European Commission and national agencies as part of the targeted initiatives of the EU Chips Act. The implementation of the Chips JU pilot lines is expected to bridge the gap from lab to fab and will be available to a wide range of users, including academia, industry and research institutions.
The NanoIC pilot line is the result of a remarkable European cross-border collaboration. Hosted by imec (Belgium), its partners include CEA-Leti (France), Fraunhofer (Germany), VTT (Finland), CSSNT (Romania) and Tyndall National Institute (Ireland).
NanoIC targets semiconductor technologies that will shape tomorrow’s high-tech solutions. One of the main goals is to develop the process steps and modules that enable these technologies. This will result in stable ‘platform’ baseline flows with a high technology readiness level (TRL 4-6).

These technologies are situated in three research pillars:

• Advanced logic technologies
• Advanced memory technologies
• Advanced interconnect technologies

In NanoIC, Tyndall’s flexibility into materials integration will allow for rapid, short-cycle screening to reduce the cycle time in identifying and integrating highly performing materials to carry forward into IC development. Our role is to provide agile wafer scale nanofabrication and processing beyond silicon for the integration of selected new materials – Transition Metal Dichalcogenides (TMDs) and oxide semiconductor (OSC) – and FET device architectures. The goal is to develop a material platform for embedded DRAM and above IC functionality, thereby providing a key technology block to enable leading-edge ICs.

PURPOSE OF THE ROLE

The purpose of this role is to design & implement a specific research programme in association with the Principal Investigator to support the development of Tyndall’s TMD activity in the NanoIC Pilot Line. You will report to, be directed by and be under the supervision of the Principal Investigator (PI) assigned to this activity.
This role is a prestigious role which represents a step change from Post-Doctoral researcher roles. Your work will be performed in accordance with the Institute’s integrity policy and all other relevant policies.
You will have dual goals in terms of the research project and your own career development. The training and development relevant to this position will be completed within the period of your contract in which time you will continue to develop skills and competencies with respect to the role and your future career options.
The Tyndall National Institute will provide the successful candidate with the individual training and development required to build a successful Senior Researcher career.
To this end, the successful candidate will be supported in their development towards a senior researcher role within the group to lead an activity centred around novel materials for future CMOS technology. The Research Fellow will be supported in applying to relevant funding programmes to support and sustain their research activities, e.g. Science Foundation Ireland-IRC Pathway program, ERC StG/CoG, while relevant training and development opportunities at Tyndall and UCC will be used to enhance their training and development and skills needed to transition to a senior role within the group.

KEY DUTIES AND RESPONSIBILITIES

• Work with the supervisor and other team members in idea and strategy generation to deliver the outputs of the project and to contribute to raising the profile of this activity
• Coordinate and execute the implementation of experimental work such as semiconductor processing, device and material metrology, presentation and interpretation of data. Specifically, for NanoIC these include:
• Conduct literature review on TMD materials and field-effect transistor (FET) devices to benchmark new data against existing knowledge.
• Fabricate thin-film TMD electronic devices, and FET and Dynamic Random Access Memory (DRAM) figures of merit.
• Draw conclusions on device figures of merit extracted, based on semiconductor device physics.
• Explore to what extent integration and fabrication affect the electrical behaviour in TMD-based devices, and correlate with material properties through hybrid metrology.
• Utilise an independent approach to carry the project work forward including to proactively identify opportunities for external funding sources, prepare grant proposals and the assessment of research findings for potential commercial exploitation in collaboration with the PI.
• Collaborate with project partners, internal and external researchers and carry out any administrative and management work associated with the NanoIC technical deliverables
• Support access to Tyndall’s offer within NanoIC as required by the Pilot Line access model for external users.
• Engage in the dissemination of the results to the relevant research stakeholders in the appropriate form such as reports result to team leaders, partners, and funding agencies and publications in the top-tier journals and at leading conferences in the field.
• Supervise and provide day-to-day advice, support, mentoring, and assistance to research graduates, students and other junior members, and contribute to the supervision of postdoctoral staff in the subject of TMD devices.
• Communicate the benefits of the research to wider society through active participation in several Education and Public Engagement activities, as required.
• Engage in appropriate training and development opportunities to develop own transferable skills, career and reputation.
• Ensure all activities are compliant with the Tyndall Quality Management system.
• Ensure all activities are compliant with the required Health and Safety standards.
• Carry out any additional duties as may reasonably be required within the general scope and level of the post.