RFIC Layout Engineer at Apple

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

31 Dec, 25

Salary

0.0

Posted On

02 Oct, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RFIC Layout, Custom RF/Analog Layout, Deep Sub-Micron CMOS, Electromigration, Signal Path Check, Differential Matching, Top-Level Layout Integration, Layout Techniques, Device Matching, Minimizing Parasitics, High-Frequency Routing, Guard Rings, CALIBRE DRC, CADENCE Layout Tools, Scripting Skills, Communication Skills

Industry

Computers and Electronics Manufacturing

Description

Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what’s considered feasible? As part of an outstanding `team, you’ll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you’ll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide. DESCRIPTION Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering. - Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block-level and top-level floorplanning. - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling. - Top-level layout integration and verification, schedule management. MINIMUM QUALIFICATIONS BS and 3+ years of relevant industry experience. Good understanding of RC delay, electromigration, and coupling. Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience). Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to work with multi-functional teams. PREFERRED QUALIFICATIONS Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing. Solid understanding of RC delay, electromigration, and coupling. Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology. Extensive knowledge of CADENCE layout tools. Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus.

Responsibilities

The RFIC Layout Engineer will be responsible for block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking. The role involves collaborating with designers on floorplanning and conducting layout reviews for various aspects such as power routing and signal coupling.