PREFERRED EXPERIENCE:

• Digital design engineering experience
• Excellent knowledge of Verilog, System Verilog, C and a scripting language; experience with Python, Perl and TCL is a plus
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Knowledge of clocking architectures, synchronization, and CDC methodology
• SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Strong understanding of computer organization/architecture.
• Mixed signal RTL experience is a plus
• Exposure to leadership or mentorship is an asset

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_

THE ROLE:

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

KEY RESPONSIBILITIES:

• Microarchitectural design and RTL implementation of IP features.
• PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
• Collaborate with Firmware team to develop firmware sequences and algorithms
• Analyze RTL design for power optimization and timing optimization
• Collaborate with Design Verification team to execute on design features Timing Synthesis & Drive Physical implementation
• Participate in design specification and RTL code reviews.