RTL Design Engineer at Advanced Micro Devices, Inc

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

25 May, 26

Salary

0.0

Posted On

24 Feb, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Rtl Design, Verilog, Systemverilog, Digital Design, Microarchitecture, Data Fabric, Lint, Cdc, Rdc, Timing Closure, Synthesis, Perforce, Git, Asic Design, Cache Coherency, Noc Design

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivatived RTL design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture of components of the Infinity Data Fabric Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data centre application systems. Collaborating with verification and integration teams to resolve inter IP integration issues Design flow quality checks - Lint, CDC, RDC and others Timing closure - timing constraints, synthesis, logic-depth reduction Design area optimizations PREFERRED EXPERIENCE: 4 + years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Knowledge of cache coherency and /or fabric /NOC design is a plus Version control systems such as Perforce, Git ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves digital design implementation and micro-architecture of components for the Infinity Data Fabric, including RTL coding in Verilog/SystemVerilog for data fabric features scaling for server and data center applications. Responsibilities also include collaborating with verification teams and performing design flow quality checks like Lint, CDC, and RDC, alongside achieving timing closure.