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RTL Design Engineer at Apple

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Jan, 26

Salary

0.0

Posted On

22 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Mixed Signal Concepts, Verilog, System-Verilog, Design Verification, Synthesis, Static Timing, DFT, System-Verilog Assertions, Checkers, SerDes, Algorithm Development, Scripting Languages, Perl, Python, Communication Skills, Collaboration Skills

Industry

Computers and Electronics Manufacturing

Description

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. In this role, you will gain the opportunity to specify, design, and contribute in the verification and lab bring-up of advanced mixed-signal circuits (digital side). DESCRIPTION In this job you will gain the opportunity to specify micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc. MINIMUM QUALIFICATIONS BS degree in technical discipline with minimum 10 years of relevant experience PREFERRED QUALIFICATIONS Deep understanding of mixed signal concepts, along with RTL design fundamentals Deep knowledge of Verilog and System-Verilog Experience with front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Working knowledge of synthesis, static timing, DFT is a huge plus Some working experience with System-Verilog assertions, checkers, and other design verification techniques Knowledge of SerDes, algorithm developments, scripting languages such as Perl and Python are plusses Strong communication, collaboration and presentation skills

Responsibilities

You will specify micro-architecting digital blocks in advanced mixed-signal circuits and be responsible for RTL coding of those blocks. Additionally, you will participate in design verification and lab bring-up of circuits.