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RTL Design Engineer at Apple

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Jan, 26

Salary

0.0

Posted On

22 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Mixed Signal Concepts, RTL Design Fundamentals, Verilog, System-Verilog, Front-End Tools, Synthesis, Static Timing, DFT, System-Verilog Assertions, Design Verification Techniques, Scripting Languages, Perl, Python, Algorithm Developments, Communication Skills, Presentation Skills, SERDES Knowledge

Industry

Computers and Electronics Manufacturing

Description

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and uncommonly hardworking RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. In this role, you will have the opportunity to specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side). DESCRIPTION In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc. MINIMUM QUALIFICATIONS BS degree in technical discipline with 10+ years of experience. PREFERRED QUALIFICATIONS Deep knowledge of mixed signal concepts Deep knowledge of RTL design fundamentals Deep knowledge of Verilog and System-Verilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Working knowledge of synthesis, static timing, DFT is a huge plus Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques Deep knowledge of scripting languages. Perl and Python are plusses Deep knowledge of Algorithm developments Strong communication and presentation skills SERDES knowledge is a plus

Responsibilities

You will be responsible for specifying and micro-architecting digital blocks in advanced mixed-signal circuits. Additionally, you will participate in the design verification and lab bring-up of these blocks.