Required Skills & Qualifications:

• Bachelor's Degree in Computer Engineering, Electrical Engineering or equivalent
• 5+ yr. working experience with FPGA/RTL design
• Verilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilog
• Xilinx FPGA(s). Specifically, Zynq and UltraScale
• Solid understanding of timing principles, including clock domain crossing and timing closure
• Strong scripting skills (e.g Python, Tcl, csh/bash, etc.)
• Experience with FPGA tools (e.g Vivado, Quartus), HDL Simulation Tools (ModelSim)

Bonus Points:

• Masters of Science in Computer/Electrical Engineering, or equivalent
• Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM
• Experience with memory mapped interfaces such as AXI, Wishbone, Avalon
• Experience with high-speed transceivers for protocols such as JESD204B, PCIe, SATA
• Experience with Linting tools, Questa Sim or Riviera-Pro
• Experience with Xilinx Versal and RFSoC 
• Experience designing printed circuit boards
• Knowledge of radio-frequency electronics design

Salary Range: $131,00 - $181,000 CAD