RTL Design & IP Release Engineer at CAPGEMINI ENGINEERING
berlin, Berlin, Germany -
Full Time


Start Date

Immediate

Expiry Date

06 Jan, 27

Salary

45000.0

Posted On

09 Oct, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Industry

Electrical Equipment Manufacturing

Description

Must Have:

  • RTL integration, ASIC design 2. CDC, Lint 3. Verilog/system verilog 4. AMBA protocols 5. scripting
  • DesignSync
  • Linux
  • Scripting
  • Verilog

Nice To Have:

  • IP release flow
  • Physical Verification
  • Python

Responsibilities
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