RTL Design & IP Release Engineer at CAPGEMINI ENGINEERING
berlin, Berlin, Germany -
Full Time


Start Date

Immediate

Expiry Date

15 Jan, 27

Salary

50000.0

Posted On

17 Oct, 26

Experience

1 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Industry

Electrical Equipment Manufacturing

Description
  • Must Have: RTL integration, ASIC design 2. CDC, Lint 3. Verilog/system verilog 4. AMBA protocols 5. scripting
  • DesignSync
  • Linux
  • Scripting
  • Verilog
  • Nice To Have:IP release flow
  • Physical Verification
  • Python

Responsibilities
Loading...