RTL Performance Analysis Architect at Qualcomm Technologies Inc Turkey

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

14 Feb, 26

Salary

0.0

Posted On

16 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Computer Architecture, Microarchitecture, Analytical Thinking, Digital Design, Performance Analysis, Memory Controller, CXL, MMU, Graphic Pipeline, Design Analysis, Cache Hierarchy, Interconnect Design, Image Compression Algorithms, SV/UVM, Performance Verification, Benchmarking

Industry

Telecommunications

Description

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: The candidate will be part of the Infrastructure IP Performance modelling, verification, and analysis team (Bangalore), working on performance verification and analysis. The team in Bangalore is part of a larger global performance team responsible for the Infra IP hardware performance. Our team is engaged in all stages of architecture development, from early-stage analysis and micro-architecture research/development to power/performance correlation vs. RTL and performance tuning efforts on production hardware. This specific role involves RTL based performance analysis and micro-architectural analysis of memory controller, last level cache and complex interconnect design for Snapdragon based SoCs including premium tier. This includes analyzing the micro-architecture to bring-out the performance bottlenecks as well as propose the design optimizations to improve it further in next generation products. The role provides an opportunity to demonstrate innovations through patents and publications. In addition, the team also focuses on cache hierarchy, CXL, MMU, Image compression algorithms and interconnect design analysis for Qualcomm mobile systems. The team has strong and proven impact to Qualcomm mobile system architecture. The team is also contributing to Qualcomm’s patent portfolio through this impact work. Responsibilities Characterize performance of applications and benchmarks to identify key CPU, GPU, multi-media, SMMU, CXL, NoC and cache controller performance bottlenecks w.r.t memory controller. Engage with architects and design teams to investigate next-generation memory controller, last level cache and interconnect microarchitecture. Key interest to analyze, identify and propose ways go towards the best PnP friendly design and architecture Develop targeted pre-silicon performance verification/analysis strategy including test plan to identify bottlenecks in the design. Develop simulation size workloads for pre-silicon performance analysis in SV/UVM platform. Job Requirements Bachelor’s degree in engineering, Information Systems, Computer Science, or related field. Excellent foundation in computer architecture, microarchitecture and strong analytical thinking 4-8 years of experience in design/performance analysis/functional verification Experience in digital design/micro-architecture experience is an added advantage for this role. Knowledge of Memory Controller, LPDDR & DDR protocols, CXL, MMU, Graphic pipeline is a plus. Experience with performance analysis and driving microarchitecture investigations on blocks like memory controller, CPU, GPU, NoC an multi-media. Strong design analysis skills to identify performance bottlenecks in the system. Desirable skills and experience Knowledge of AMBA and ARM architecture-based systems Understanding of system performance use cases or relevant background Right attitude to work in a highly competitive team Minimum Qualifications: • Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

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Responsibilities

The candidate will characterize performance of applications and benchmarks to identify performance bottlenecks in memory controllers and interconnect designs. They will engage with architects and design teams to investigate next-generation microarchitecture and develop pre-silicon performance verification strategies.