Senior Analog Layout Engineer at NXP Semiconductors

Kuala Lumpur, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

20 Jun, 26

Salary

0.0

Posted On

22 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Analog Layout, AFEs, ADCs, DACs, PLLs, Voltage Regulators, DRC, LVS, ERC, PEX Extraction, Cadence Virtuoso, Calibre, Device Matching, Parasitic Control, EM/IR, CMOS Technologies

Industry

Semiconductor Manufacturing

Description

Key Responsibilities Custom Analog Layout Execution Perform full‑custom analog layout for critical circuit blocks, including: Analog Front Ends (AFEs) ADCs and DACs PLLs and clocking circuits Voltage regulators and references Analog filters and bias circuits Translate schematics into high‑quality, silicon‑proven layouts in advanced nodes. Apply best‑in‑class techniques for: Matching and symmetry Parasitic control Noise isolation and substrate coupling mitigation EM/IR and reliability robustness Verification & Sign‑off Run and debug DRC, LVS, ERC, and reliability checks. Work with designers to close LVS and performance issues. Support PEX extraction and simulation correlation. Ensure layouts meet foundry design rules and sign‑off requirements. Collaboration & Production Support Partner closely with analog circuit designers, CAD, and methodology teams. Participate in layout and design reviews. Support silicon bring‑up, debug, and yield improvement as needed. Contribute to layout guidelines, documentation, and best practices. Required Qualifications Education BSEE or equivalent in Electrical / Electronics Engineering (preferred). Experience 6–10 years of hands‑on experience in custom analog / mixed‑signal layout. Proven experience working in 28nm, 22nm, and/or 16nm CMOS process technologies. Demonstrated experience laying out complex analog IP blocks (AFE, ADC, DAC, PLL, regulators). Tools & Methodologies Strong proficiency with: Cadence Virtuoso Layout Suite Calibre (DRC, LVS, PEX) Solid understanding of: Foundry design rules Device matching and layout‑dependent effects Parasitics, coupling, and noise mitigation Reliability (EM, IR, ESD awareness) Familiarity with advanced-node layout challenges is required. Preferred Qualifications Experience in automotive or high‑reliability semiconductor products. Familiarity with low‑noise, high‑speed analog layouts. Ability to mentor junior layout engineers. Exposure to ISO / automotive quality flows is a plus. More information about NXP in Malaysia... #LI-633a NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality. Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips. Are you already an NXP employee? Do not apply here. Instead, you must apply via our internal career page. Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise. Thank you for your understanding.

Responsibilities

The Senior Analog Layout Engineer will perform full-custom analog layout for critical circuit blocks like AFEs, ADCs, DACs, and PLLs, translating schematics into high-quality layouts in advanced nodes. Key tasks include applying best-in-class techniques for matching, parasitic control, noise isolation, and ensuring reliability robustness through verification and sign-off.