Senior Analog Layout Engineer at NXP Semiconductors

Catania, Sicily, Italy -

Full Time

Start Date

Immediate

Expiry Date

03 Aug, 26

Salary

0.0

Posted On

05 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Analog Layout, Mixed-Signal Design, Cadence Virtuoso, Mentor Graphics Calibre, Physical Verification, Floorplanning, Device Physics, ESD Protection, LVS, DRC, ERC, Parasitic Extraction, DFM, SoC Integration, Technical Mentoring, English Fluency

Industry

Semiconductor Manufacturing

Description

High Performance Analog (HPA) PL is looking for a Senior Layout Design Engineer who will be responsible for chip and block level layout of high-performance analog and mixed-signal products. A successful candidate will operate as the lead layout design engineer for the PL. The candidate will set up and debug LVS, DRC, ERC environments for the project team, as well as collaborate with lead chip design engineer on chip-level floor-plan. In addition, the candidate will layout critical building blocks such as high-resolution (e.g. 24-bit) analog-to-digital converters, precision voltage references, and HV chopper-stabilized amplifiers. As the lead layout design engineer of the PL, the candidate will also mentor fellow layout design engineers on techniques and best practices for high-precision and low-noise analog designs. As a key member of the team, you will be responsible for: · Driving/delivering floorplan activities at both IPs and/or SOC level. · Participating to the power supply strategy, signals distribution between blocks. · Delivering Analog layout blocks and/or top floorplan strategy. · Driving the top-level integration using the Mixed Signal on Top flow. · Leading a layout team for the SoC execution and scheduling its activities through the project. · Running all physical verifications as DRC/LVS/DFM and parasitic extractions to achieve high quality layout deliveries. · Participating to design reviews, write documentation and support for integration into products. · Having a strong focus on design for quality (designs are properly verified, validated, and tested for long-term reliability and zero defect). · Identifying root cause and solutions for issues identified on 1st prototypes. · Being able to leverage layout expertise to provide technical training and write technical guidelines. The ideal candidate will have: · >10+ years of experience leading Analog layout activities in complex ICs. · Fluent in English. · Strong expertise in Analog layouts, device physics and IC ESD protection strategies. · Expert in layout design tools such as Cadence Virtuoso (OA, PVS) and Mentor Graphics (Calibre). · Ability to drive and collaborate with experienced people having different technical profiles. · Ability to manage and drive a multisite layout team. · Experience in delivering advanced floorplan strategies. · Experience in physical implementation in Analog blocks at IPs and/or SOC level. · Ability to leverage his expertise to provide training, support and write guidelines focused on layout activities. · Experience with cross functional teams and excellent communication skills to operate in a global environment with multiple partners in design, test, program management, quality department. More information about NXP in Italy... #LI-7795 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality. Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips. Are you already an NXP employee? Do not apply here. Instead, you must apply via our internal career page. Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise. Thank you for your understanding.

Responsibilities

Lead the chip and block level layout for high-performance analog and mixed-signal products, including floorplanning and physical verification. Mentor other layout engineers and drive the top-level integration using Mixed Signal on Top flow.