Senior ASIC Design Engineer (NetSec) at Palo Alto Networks

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

16 Mar, 26

Salary

235000.0

Posted On

16 Dec, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design, SystemVerilog, RTL, Verification, Debugging, Scripting, Micro-Architecture, Datapath Design, Timing Analysis, Power Analysis, Collaboration, Communication, Networking, Cybersecurity, Silicon Validation, AI-Driven Design

Industry

Computer and Network Security

Description

Company Description Our Mission At Palo Alto Networks® everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are. Who We Are We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes. Job Description Your Career Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design engineers to hit aggressive performance, power, and schedule goals. Your Impact Write clear design and micro-architecture specifications. Design SystemVerilog RTL that meets area, performance, and power targets. Verify your blocks with simulation, emulation, formal methods, and silicon bring-up. Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features. Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability. Innovate: pilot AI-driven design or verification flows that cut schedule risk. Qualifications Your Experience BS in EE, CE, or CS (MSEE or equivalent military experience preferred). 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production. Solid experience with PCIe core integration and lab validation. Expert SystemVerilog RTL skills. Scripting proficiency (Python, C/C++, Perl, bash or tcsh). Demonstrated strength in: Defining micro-architecture from high-level requirements. Datapath design expertise for intricate synch/asynch digital logic. Debugging across simulation, emulation, and silicon. Analyzing timing, power, and area reports and driving fixes. Excellent leadership, collaboration, and written/verbal communication. Preferred / Nice-to-Have Networking or cybersecurity domain knowledge. Experience with DDR5 memory, Ethernet (IEEE 802.3), or search-algorithm accelerators. Formal-verification ownership. Hands-on silicon validation and lab bring-up. Additional Information The Team We are the global cybersecurity leader, known for always challenging the security status quo. Our mission is to protect our way of life in the digital age by preventing successful cyberattacks. This has given us the privilege of safely enabling tens of thousands of organizations and their customers. Our pioneering Security Operating Platform emboldens their digital transformation with continuous innovation that seizes the latest breakthroughs in security, automation, and analytics. By delivering a true platform and empowering a growing ecosystem of change-makers like us, we provide highly effective and innovative cybersecurity across clouds, networks, and mobile devices. Our Security Operating Platform is built for automation. It is easy to operate, with capabilities that work together, so customers can prevent successful cyberattacks. They can use analytics to automate routine tasks, so they can focus on what matters. We are known for continuously delivering innovations; and with Application Framework, we extend that to an open ecosystem of developers that benefit from our customers’ existing investment in data, sensors, and enforcement points. Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $166000/YR - $235000/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here. Our Commitment We’re problem solvers that take risks and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together. We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [email protected]. Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics. All your information will be kept confidential according to EEO guidelines.

Responsibilities

The Senior ASIC Design Engineer will own module design from specification through silicon bring-up, collaborating with verification and physical-design engineers. Responsibilities include writing design specifications, designing RTL, verifying blocks, and innovating design flows.