Senior ASIC Designer at CO-WORKER TECHNOLOGY

Norrtälje kommun, , Sweden -

Full Time

Start Date

Immediate

Expiry Date

19 Jan, 26

Salary

0.0

Posted On

21 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design, SoC Design, RTL Design, Microarchitecture, Verification, Simulation, Synthesis, Static Timing Analysis, Architectural Design, System Integration, Low Power, DFT, Modeling, High-Level Design, Scripting, Automation, Leadership

Industry

Staffing and Recruiting

Description

Assignment description:Professional Experience 8–15+ years of experience in ASIC/SoC design and development. Demonstrated ownership of multiple ASIC projects from specification to tape-out and bring-up. Proven leadership in defining and delivering system and chip architectures. Technical Expertise RTL & Microarchitecture Expert-level proficiency in Verilog/SystemVerilog for RTL design. Solid experience developing microarchitecture specifications for complex subsystems. Familiarity with clocking, resets, power domains, FSMs, pipelining, and parallelism. Verification & Simulation Good understanding of functional verification methodologies (SystemVerilog, UVM). Ability to collaborate with verification teams on test plans, assertions, and coverage. Familiar with simulators (e.g., VCS, Questa, ModelSim). Synthesis & Static Timing Analysis Hands-on experience with logic synthesis tools (Synopsys Design Compiler, Cadence Genus). Skilled in timing constraint definition (SDC) and timing closure using PrimeTime. Able to guide physical design teams on floorplanning, congestion, and timing paths. Architectural Design & System Integration Ability to define and document chip-level architecture, including: Block diagrams, interface protocols (AXI, PCIe, Ethernet, etc.). Data and control flow, memory hierarchies, and DMA engines. Power, performance, area (PPA) trade-off analysis. Skilled in specification development: architectural specs, ICDs, design guides. Low Power & DFT Knowledge of UPF/CPF, clock gating, power domains, DVFS. Familiar with DFT techniques: scan chains, MBIST, boundary scan (useful for collaboration with DFT teams). Modeling & High-Level Design Experience with performance modeling using Python, C/C++, SystemC. Capability to run system-level simulations and evaluate architectural choices. (Optional) Familiarity with High-Level Synthesis (HLS) flows. Scripting & Automation Proficiency in Python, Perl, or Tcl for design and flow automation. Soft Skills & Leadership Strong debugging and problem-solving skills across RTL, synthesis, and system levels. Capable of leading cross-functional teams including design, verification, physical design, firmware, and software. Experience mentoring junior engineers and reviewing their designs. Excellent verbal and written communication for documenting specs and collaborating with stakeholders. Bonus Qualifications Knowledge of AI/ML accelerators, networking, or video processing pipelines. Experience with multi-die (chiplet) integration, 2.5D/3D packaging. Understanding of security architectures, encryption modules, or hardware IP protection. Background in post-silicon validation, lab bring-up, or FPGA prototyping. Exposure to embedded firmware/software, drivers, or hardware-software co-design.

Responsibilities

The Senior ASIC Designer will lead multiple ASIC projects from specification to tape-out and bring-up, demonstrating ownership and leadership in defining system and chip architectures. The role requires collaboration with cross-functional teams to ensure successful project delivery.