Senior ASIC Power Engineer, ML Accelerators at Google

Sunnyvale, California, United States -

Full Time

Start Date

Immediate

Expiry Date

29 Mar, 26

Salary

229000.0

Posted On

29 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design, Power Management, RTL Design, Verilog, SystemVerilog, Low-Power Design, Power Optimization, Chip Design, Digital Design, AI, ML, TPU, Computer Architecture, Power Modeling, Thermal Management, System-Level Tradeoffs

Industry

Software Development

Description

MINIMUM QUALIFICATIONS: * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 5 years of experience in logic design, digital ASIC, or SoC design. * Experience with RTL (Register Transfer Level) design using Verilog or SystemVerilog. * Experience with low-power design or power reduction methodologies/techniques. PREFERRED QUALIFICATIONS: * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. * Experience defining and implementing chip-wide power management architectures and designs. * Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases. * Understanding of modern power and thermal management techniques at both the silicon and system levels (including DVFS, Turboing, Thermal Management, and system-level tradeoffs). * Ability to solve open-ended power and performance problems under ambiguity. ABOUT THE JOB: In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will play a pivotal part in improving the power efficiency of our Tensor Processing Units (TPUs). You will drive power efficiency for our TPU designs, starting from building power models to proposing novel power optimization techniques. You will utilize background in modeling and optimizing chip power, as well as have an understanding of system level power considerations and tradeoffs. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google [https://careers.google.com/benefits/]. RESPONSIBILITIES: * Contribute to design power modeling and drive convergence to power goals. * Investigate, specify, and deploy architectural and microarchitectural power optimization techniques. * Define best practices and methodologies to achieve low-power RTL designs. * Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.

Responsibilities

Contribute to design power modeling and drive convergence to power goals. Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.