Senior Design Engineer - Memory Subsystem at NVIDIA

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

30 Aug, 26

Salary

0.0

Posted On

01 Jun, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Micro-architecture, RTL Development, Verilog, ASIC Design Flow, Logic Synthesis, Timing Analysis, Floor-planning, Post-silicon Verification, Python, Perl, Shell Scripting, VCS, Debussy, GDB, Memory Subsystem, Network Interconnect IP

Industry

Computer Hardware Manufacturing

Description

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of a team working on the design of state of the art memory sub-system components used in their industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” In this position, you will be encouraged to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks. What you’ll be doing: Own micro-architecture and RTL development of design modules. Micro-architect features to meet performance, power and area requirements. Work with HW architects to define critical features. Collaborate with verification teams to verify the correctness of implemented features. Interact with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Co-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 4+ years of design experience. Experience in micro-architecture and RTL development of complex designs. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping,, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in memory subsystem or network interconnect IP. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a part of a team. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.

Responsibilities

Own the micro-architecture and RTL development of memory subsystem components for GPUs and SOCs. Collaborate with architects, verification, and physical design teams to deliver synthesis and timing clean designs.