Senior Design Engineer at Microsoft

Redmond, Washington, United States -

Full Time

Start Date

Immediate

Expiry Date

25 Feb, 26

Salary

0.0

Posted On

27 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Design, Microarchitecture Specification, RTL Coding, Verilog, System Verilog, Clock Domain Crossing, Lint Closure, Synthesis, Timing Constraints, Power, Performance, Area Trade-offs, Post-Silicon Debug, SOC Integration, System Verilog Assertions, Scripting Languages, Tapeouts

Industry

Software Development

Description

You will be part of the design team driving many facets of high performance, high bandwidth Network-on-Chip designs in the start-of-the-art AI SoCs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 4+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs. 4+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure. 4+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug 4+ years of experience with Synthesis, Standard Design Constraints (SDC) and Unified Power format UPF 4+ years of experience working on SOC integration Experience with industry standard interfaces such as Advanced extensible Interface (AXI), APB, JTAG Experience with writing System Verilog assertions and coverpoints Experience with scripting languages such as Perl or Python Track record of successful tapeouts in deep sub-micron technologies Ability and willingness to adapt and work on variety of designs

Responsibilities

You will be part of the design team driving high performance, high bandwidth Network-on-Chip designs in AI SoCs. You will interact with various teams to ensure the design is implemented and verified to the specifications.