Senior Design Verification Engineer at Condor Computing

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

02 Jan, 26

Salary

0.0

Posted On

04 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, UVM, SystemVerilog, Event-Driven Simulation, Low-Power Implementation, Scripting Languages, Chip Architecture, Collaboration, Communication

Industry

Semiconductor Manufacturing

Description

Condor Computing is a brand-new member of the RISC-V revolution. Condor is aiming to fly high by building the industry’s highest performance licensable RISC-V core. Our team of highly experienced CPU designers will create a new benchmark for power efficiency in high performance open-source computing. We are pleased to announce that Condor is seeking a skilled and personable Sr. DV Engineer to become a valuable member of our team. In this position, you will have the opportunity to investigate innovative strategies to enhance the performance of our high-performance RISC-V processors, with a focus on all functions within the CPU core and memory systems. You will work collaboratively with a talented team, including engineers from RTL design, verification, and software groups, to propose enhancements, optimizations, and features based on performance assessments and PPA impact. Here is what you will do: Architect and implement testbenches utilizing UVM-based methodologies Design and develop Verification Components using UVM-based techniques Conduct block-level verification to ensure optimal block performance and compliance with requirements Generate and execute verification plans based on specifications Define, implement, and analyze coverage metrics Architect and implement Formal Verification processes Create automation tools to streamline testing Perform testing for design performance evaluation Here is the background we hope you have: A Master's or Bachelor's degree in Electronic/Electrical Engineering or Computer Science 8+ years of experience in Verification Proven industry experience in developing testbenches and verification components with SystemVerilog and UVM from inception In-depth knowledge of event-driven simulator-based modeling techniques Experience with low-power implementation (UPF) Familiarity with scripting languages such as Python, Ruby, or Perl A comprehensive understanding of chip and/or computer architecture These would be nice to have but are not required: Strong written and verbal communication abilities Exceptional collaboration skills across sites and functions Condor Computing is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application!

Responsibilities

You will architect and implement testbenches utilizing UVM-based methodologies and conduct block-level verification to ensure optimal block performance. Additionally, you will work collaboratively with a talented team to propose enhancements and optimizations based on performance assessments.