Start Date
Immediate
Expiry Date
17 Jun, 26
Salary
0.0
Posted On
19 Mar, 26
Experience
2 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
SystemVerilog, UVM, Verification Plan, TestBench Development, Functional Coverage, SystemVerilog Assertion, Constrained-Random Verification, Debugging, Verilog, C++, TCL, PERL, RTL Coding, Object-Oriented Language, Digital Logic, Circuit Design
Industry
Semiconductor Manufacturing