Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft’s over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
As Microsoft’s cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Design Verification Engineer.

REQUIRED QUALIFICATIONS:

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
• Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
• OR equivalent experience.
• 5+ years of experience in developing test plans, creating simulation environments, developing tests, or debugging for multiple IPs, SoCs or systems.
• 4+ years of experience with SystemVerilog/Verilog, VHDL or C/C++.

OTHER REQUIREMENTS:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

PREFERRED QUALIFICATIONS:

• In depth knowledge of verification principles, testbenches, stimulus generation.
• Substantial background in creating simulation environments, developing tests or debugging designs
• Knowledge of AXI protocol
• Experience with Coverage Closure
• Proven understanding of chip and/or computer architecture
• Experience writing tests in C/C++ or UVM
• Proficiency in scripting languages such as Python, Ruby, or Perl
• Excellent communication skills
• Energetic and self-motivated
• Verification with UVM based test environments
• Experience in debugging Subsystems/SOCs scenarios with embedded processors
• Experience with secure hardware design for embedded systems
• Experience with hardware emulation or FPGAs
• Experience in RTL design for FPGA or emulation
• Experience in Assembly, start up code and linker scripts
• Experience in developing makefiles for software development
  Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
  Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay.
  Microsoft will accept applications for the role until August 17, 2025.

• Develop Test Plans and review with appropriate stakeholders (architecture, design, verification)
• Work with cross-discipline teams (systems, firmware, architecture, design, verification, validation, product engineering, …) to create environment and test cases to verify Subsystem/IP Designs
• Debug environment/test cases