Engineering - Leuven | Just now

What you will do

• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/R(epair), OPCG (OCC) for large-scale low-power designs in advanced nodes (7nm and beyond).
• Generate test patterns, debug/improve fault coverage, support debug of post-silicon test patterns.

• Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.Work closely with Test engineering team on silicon characterization and validation.

• What we do for you
  We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
  We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, ’our corporate university’, we actively invest in your development to further your technical and personal growth.
  We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• 5+ years of experience in digital ASIC design, 10+ years of experience with DFT insertion and ATPG.
• Basic fluency with Verilog/VHDL to write code for test logic when needed.
• Hands-on experience with defining SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, est debug, for large low-power designs in advanced nodes (7nm and beyond).
• Experienced in EDA tools such as Genus/Modus (Cadence) and Tessent (Siemens), and simulation tools.
• Experienced in scripting languages especially TCL.
• Knowledge of IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL) is a plus.
• Experience in a design on advanced nodes with hierarchical DFT requirements is a plus.

IMEC and its affiliates will not accept unsolicited resumes from any source other than directly from a candidate. IMEC will consider unsolicited referrals and/or resumes submitted by vendors such as search firms, staffing agencies, professional recruiters, fee-based referral services and recruiting agencies (hereafter “Agency”) to have been referred by the Agency free of charge. IMEC will not pay a fee to any Agency that does not have a prior written agreement with IMEC, validated by its HR department, in place regarding a specific job opening and allowing to submit resumes.

• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/R(epair), OPCG (OCC) for large-scale low-power designs in advanced nodes (7nm and beyond).
• Generate test patterns, debug/improve fault coverage, support debug of post-silicon test patterns.
• Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.Work closely with Test engineering team on silicon characterization and validation