Senior DFT Engineer at Microsoft

Raleigh, North Carolina, United States -

Full Time

Start Date

Immediate

Expiry Date

09 Apr, 26

Salary

234700.0

Posted On

09 Jan, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DFT Architecture, Scan Insertion, Boundary Scan, MBIST, JTAG, ATPG, Pattern Generation, Post-Silicon Debug, Test Program Development, Failure Analysis, DFT Automation, Manufacturing Test Compliance, Siemens DFT Tools, Debug Skills, RTL Simulation, Gate Level Simulation

Industry

Software Development

Description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence SOC team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior DFT Engineer to join the team. Responsibilities Execution across multiple projects, ensuring alignment with overall chip design goals. Define and implement DFT architecture, including scan insertion, boundary scan, MBIST, and JTAG. Collaborate with RTL, physical design, and verification teams to integrate DFT features seamlessly. Manage ATPG and pattern generation, ensuring high fault coverage and test efficiency. Oversee post-silicon bring-up and debug, including test program development and failure analysis. Drive tool and flow development for DFT automation and optimization. Ensure compliance with manufacturing test requirements, including support for ATE platforms. Track project milestones and deliverables, reporting status and risks to leadership. Evaluate emerging DFT methodologies and tools, recommending improvements to enhance test quality and productivity. Qualifications Required/minimum qualifications Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Additional or Preferred Qualifications Excellent debug skills for RTL and gate level simulations Experience in DFT scan insertion and or Custom Memory BIST design and verification. Experience with Siemens DFT tools. Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Responsibilities

The Senior DFT Engineer will execute across multiple projects, ensuring alignment with chip design goals and defining DFT architecture. Responsibilities include managing ATPG, overseeing post-silicon bring-up, and driving tool development for DFT automation.