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Senior DFT Engineer at onsemi

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

23 Jul, 26

Salary

0.0

Posted On

24 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DFT, ASIC, SoC, Scan, ATPG, MBIST, JTAG, RTL, Physical Design, STA, Test Engineering, CDC, Low-power design, Silicon bring-up, Fault coverage

Industry

Semiconductor Manufacturing

Description

About the Role onsemi is seeking a DFT Engineer to support the design and implementation of Design‑for‑Test (DFT) features for complex ASIC/SoC products across automotive and industrial applications. This role focuses on scan, ATPG, MBIST, and boundary scan, with close collaboration across design, PD, and test teams. Key Responsibilities * Develop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG * Implement and debug DFT logic to ensure high fault coverage and test quality * Generate and analyze ATPG patterns using industry‑standard tools * Support at‑speed and transition fault testing * Collaborate with RTL, Physical Design, STA, and Test Engineering teams * Address timing, CDC, and low‑power DFT considerations * Support test coverage analysis, DFT signoff, and silicon bring‑up * #LI-RT1 onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. More details about our company benefits can be found here: https://www.onsemi.com/careers/career-benefits [https://www.onsemi.com/careers/career-benefits] We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

Responsibilities

Develop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG for complex ASIC/SoC products. Collaborate with cross-functional teams including RTL, Physical Design, and Test Engineering to ensure high fault coverage and successful silicon bring-up.