Senior DfX Engineer at Ericsson

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

14 Jan, 26

Salary

0.0

Posted On

16 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Dfx, Soc, Asic Design, Dft, Dfd, Dfm, Verification, Test Strategy, Physical Design, Eda Vendors, Cad Team, Automation, Post Silicon Debug, Yield Bring Up, Test-Time, Pattern Delivery

Industry

Telecommunications

Description

Grow with us Senior DFX Engineer, Austin, Texas This is not a remote opportunity. Ericsson Inc. does not sponsor US work authorizations for this job position including H-1B, O-1, and TN. Ericsson also does not hire F-1's working on EAD for this position. About this Opportunity The Ericsson Radio and Baseband Products have our ASICs as their backbone, and our challenge is to design and deliver those so that our 5G leadership position in the market accelerates. Our ASICS are challenging when considering the overall combination of Size/complexity, Test Quality & Reliability, Power, Performance targets, advanced process node technology, and pushing the design methodology on an ongoing basis. We are looking for a DFX Engineer to join us and be a part of this newly formed & very experienced DFX team. The role will help build the DFX team further, define strategy for long term, including all aspects of DFX (Architecture, Design, Verification, Methodology, Test, Silicon Debug). It includes working closely with other functions within Austin and in Sweden as the design takes shape at the IP, SOC, and system level to ensure that the final ASIC achieves the program goals. You will also work closely with our partners and other sites as we continue to build out our capability as we compete with What you will do Contribute to building of a world-class DFX group Strategize, architect, plan, design/implement & verify full DFT capability from scratch Partner with Test Team to define overall Test Strategy Partner with Physical Design teams (IP & SOC) to develop complex SOCs Work closely with EDA Vendors & CAD team to define next generation DFT flows and methodology with latest & greatest features Mentor & coach junior engineers within the team and helping them achieve their goals Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams What you will bring 12+ years of experience working in SOC/IP/ASIC design team with an emphasis around DFX (DFT/DFD/DFM). Experience on DFX Verification specifically (Verification of features like: Memory BIST, JTAG, Boundary Scan, In-field Tests, Custom IP Test Interface etc.) would be of great interest for this role. Minimum Education: BSEE, MSEE in equivalent area of study preferred. Must have working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency, and their impact to overall design implementation. Experience with SOC level DFT planning, architecture, and execution. Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function. Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with TEPE teams for long term strategic improvements. Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come. Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs.

Responsibilities

The role involves contributing to the building of a world-class DFX group and strategizing, architecting, planning, designing, implementing, and verifying full DFT capability from scratch. It includes collaboration with various teams to ensure the final ASIC meets program goals.