Senior Digital ASIC Design Engineer Synthesis (m/f/d) at Advantest Europe GmbH
berlin, Berlin, Germany -
Full Time


Start Date

Immediate

Expiry Date

22 Dec, 26

Salary

50000.0

Posted On

23 Sep, 26

Experience

1 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Industry

Electronics & Semiconductor Manufacturing

Description

IoT, 5G and Artificial Intelligence. Unthinkable without us. More than half of all the microchips produced worldwide first pass through our hands. As the global market leader of automated test systems in the semiconductor industry we help the world to realize the digital transformation, enable our customers to shape the future and offer you the exciting jobs intended for pioneers.You work in international teams with a high degree of personal responsibility and short communication channels.

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Responsibilities

Join a global, highly skilled engineering team at the heart of Advantest's cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing.

You will work on complex mixed signal ASICs used in Advantest's industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership.

In this role, you will collaborate closely with system architects and design engineers. You will generate constraints for synthesis of IP blocks and the chip top level integration. You will analyze critical paths for robust designs, keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale.

Job Duties & Responsibilities

  • Architecture development for CMOS designs
  • Design and RTL coding of digital and full-custom modules
  • Verification on module and chip level including test plan/cases generation.
  • Documentation of implemented functionality
  • Constraint generation and synthesis of IP blocks and the chip top level
  • Analysis of timing and power consumption
  • Support for floor planning and physical design
  • Close collaboration with design partners


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