Senior Digital Verification Engineer (CIS) at Samsung Research and Development Center Israel

Tel Aviv, Tel-Aviv District, Israel -

Full Time

Start Date

Immediate

Expiry Date

25 Jul, 26

Salary

0.0

Posted On

26 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Verification, System Verilog, UVM, Perl, Python, Verification Planning, Test Execution, Coverage Closure, Debugging, Chip Development, Electronic Engineering, IP Level Verification, System Level Verification, Regression Testing

Industry

Consumer Electronics

Description

Samsung R&D Center is looking for a Senior Digital Verification engineer. Samsung (SIRC), shaping the world of tomorrow, Today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology. Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion. The Group The Verification Cmos-Image-Sensor-Team is required to tackle the full flow of verification, from block & IP level to system level, including interfaces & deep understanding of all design flow and technical teams (such as Digital & FW). We are looking for people with a broad set of technical skills, who are ready to tackle some of technology’s greatest challenges, who have the ability to think out of the box and bring the disruptive technologies that will define our future. What will you be doing? Responsible for the full life cycle of verification, from verification planning to test execution and coverage closure. Plan the verification of complex digital designs from block level up to system level, by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Debug tests with design engineers to deliver functionally correct blocks and finalize regressions. Collaborate closely with all groups in active projects including Design, Algorithm, FW and Analog engineers. Requirements BSc. in Electronic Engineering Minimum 5 years’ experience as a verification engineer, completing at least one chip development cycle. Developed verification environments Knowledge in verification methodologies and tools Knowledge of System Verilog UVM Scripting languages knowledge (perl, python) Methodological approach to the verification tasks planning and execution

Responsibilities

Responsible for the full life cycle of verification, from planning to test execution and coverage closure. Collaborates with design, algorithm, firmware, and analog engineers to identify verification scenarios and debug tests.