Senior Digital Verification Engineer at Samsung Research and Development Center Israel

Tel Aviv, Tel-Aviv District, Israel -

Full Time

Start Date

Immediate

Expiry Date

26 Sep, 26

Salary

0.0

Posted On

28 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, UVM, Python, Perl, Bash, TCSH, Cadence Xcelium, vManager, Indago, ASIC Verification, SoC Verification, SVA, CI/CD Pipelines, MIPI, AXI, AHB

Industry

Consumer Electronics

Description

Samsung R&D Center (SIRC) is looking for an expert-level Senior Verification Engineer to join our team, focusing on the continuous improvement of our verification infrastructure. We are shaping the world of tomorrow, today—focusing beyond the horizon and driving exciting developments across key areas of technology. Samsung is creating a new era of continuous innovation, delivering value to society, and cultivating a workplace where our employees can maximize their talent, creativity, and passion. The Group The Verification Advanced Sensor Products team tackles the full verification flow for next-generation imagery sensors powering Mobile, AR/VR applications, and Automotive domains. We dive deep into complex design flows, focusing heavily on Image Signal Processor (ISP) algorithms, system control blocks, and security blocks. To support this complexity, we require a robust, scalable, and highly automated verification ecosystem. We are looking for a senior verification engineer who can architect our methodologies, optimize our toolchains, and build the infrastructure that empowers our verification teams to work faster and smarter. What You Will Be Doing Maintain, and continuously improve complex, scalable UVM-based verification environments and testbench architectures across the entire sensor portfolio. Define and drive best practices in verification methodology, ensuring high reusability, efficient coverage closure, and robust SVA strategies across block and system levels. Lead the optimization of regression environments, simulation workflows, and debug toolchains (e.g., Cadence Xcelium, vManager, Indago) to reduce turnaround time and improve resource utilization. Develop and maintain sophisticated automation frameworks and tooling pipelines using Python, Perl, and advanced shell scripting (Bash/TCSH) within a Linux environment. Support the evaluation and integration of AI tools and methodologies to accelerate test generation, automate triage, and modernize verification workflows. Serve as a technical focal point for mid-level engineers. Collaborate closely with Design, Algorithm, FW, and Analog teams to ensure the infrastructure supports all cross-functional requirements seamlessly. Requirements BSc. or MSc. in Electrical/Electronic Engineering, Computer Engineering, or a related field. Minimum of 8+ years of progressive experience in complex ASIC/SoC verification, with a proven track record of completing multiple successful tape-outs. Demonstrated experience in architecting, building, and maintaining large-scale verification environments and regression infrastructures. Deep, authoritative knowledge of SystemVerilog and advanced UVM architectures. Expert-level proficiency with industry-standard verification tools, simulators, and regression management systems (strong preference for the Cadence ecosystem). Exceptional programming and scripting skills (Python, Perl, Bash/TCSH, Makefiles) focused on workflow automation and CI/CD pipelines for hardware. Experience using AI tools to accelerate verification, improve test generation, or optimize workflows. Advantages Deep understanding of Image Signal Processor (ISP) algorithms, DMAs, or complex security blocks. Extensive experience verifying standard protocols, specifically MIPI, APB, AXI, and AHB. Background in developing products for Mobile, AR/VR, or Automotive domains, including familiarity with functional safety standards (e.g., ISO 26262). Proven experience leveraging Machine Learning or AI-assisted tools within hardware verification flows.

Responsibilities

Architect and maintain scalable UVM-based verification environments and automation frameworks for next-generation imagery sensors. Optimize simulation workflows and toolchains while leading the integration of AI tools to modernize verification processes.