WE ARE:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
Our System Solutions Group enables our customers with end-to-end SoC designs in advanced technologies. We deliver tool flows, provide expertise in design methodology creation and implementation, and support RTL-to-GDSII implementation for blocks, sub-systems, and full SoCs. Our customers range from start-ups to industry leaders, commercial and government agencies, developing products for high-performance computing, automotive, aerospace & defense, and more.

YOU ARE:

You are a seasoned design engineer with a passion for leading teams and driving complex projects to successful completion. With over 15+ years of experience in designing and verifying ASIC/FPGA devices, you excel in applying modern design processes and flows for ASIC designs. Your strong technical background is complemented by your ability to collaborate effectively with cross-functional teams. You possess a detailed understanding of the ASIC design flow, from microarchitecture through RTL development, verification, synthesis, and timing closure. Your expertise in System Verilog RTL coding and review of complex designs, along with your experience with vendor tooling within an ASIC development flow, makes you an invaluable asset to any team. You thrive in dynamic environments, constantly seeking new challenges and opportunities to innovate.

• Manage and lead a team of SoC/Subsystem Design Engineers for various customer engagements.
• Work with Synopsys customers to understand their needs and define design scope and activities.
• Lead and mentor a design team in day-to-day activities and grow the capabilities of the design team for future assignments.
• Understand and apply modern design processes and flows for ASIC designs.
• Partitioning and architecting designs from requirements, including high-level and microarchitecture.
• Collaborating with cross-functional teams, including verification, DFT, and physical design.
• Implementing industry-standard design methods for clocking, resets, metastability, and logical design for control/data paths.
• Developing and reviewing System Verilog RTL code for complex designs.