At CesiumAstro, we are developers and pioneers of out-of-the-box communication systems for satellites, UAVs, launch vehicles, and other space and airborne platforms. We take pride in our dynamic and cross-functional work environment, which allows us to learn, develop, and engage across our organization. If you are looking for hands-on, interactive, and autonomous work, CesiumAstro is the place for you. We are actively seeking passionate, collaborative, energetic, and forward-thinking individuals to join our team.
We are looking to add a Senior DSP/FPGA Engineer I to join our team. If you are great at what you do and are passionate about developing leading-edge communication solutions for satellites, spacecraft, and aerospace systems, then we would like to hear from you. The successful candidate will have experience in complex Digital Signal Processing (DSP) for communications systems, targeting high-speed efficient digital implementation in FPGA.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS

• Bachelor of Science (BSc) from an accredited university or institution. It is envisaged that the successful candidate will have more than 4 years postgraduate experience.
• A strong background in Communications Theory, with an excellent theoretical knowledge of advanced concepts in DSP and digital communication systems, and a baseline understanding of wireless modem operation.
• Strong algorithmic modelling skills using either MATLAB or Python.
• Ability to partition design problems and to define block-level hardware architectures. An excellent knowledge of VHDL is essential.
• Competence with MS Office tools to present technical information and generate concise reports.
• Solid track record of on-time and high-quality project delivery.

PREFERRED EXPERIENCE

• Higher degree in Electronics/Communications Engineering from an accredited university or institution.
• Knowledge of the real-time implementation of complex DSP in parallel processor architectures
• Good understanding of well-known Wireless Communications standards, in particular the DVB-S2(X) and CCSDS standards.
• Understanding of digital and analogue hardware design with some hands-on laboratory experience of bringing-up and validating designs, utilising various lab equipment.

• The research and design of fast and efficient hardware realisable DSP algorithms to implement functions such as filters, equalisers, timing/carrier recovery loops, multi-rate structures & FFT processing engines.
• The development of models to provide real life stimulus for testing the developed algorithms, including phase and Gaussian noise, non-linear RF effects, Doppler, multipath and other such channel impairments.
• The development of both floating- and fixed-point models in MATLAB or Python, where the fixed-point model can be directly used to accurately verify the functionality of the VHDL hardware realisation.
• Efficient and robust realisation and testing of the developed algorithms using VHDL.
• The successful candidate will be versatile and proactive, a clear communicator and team player with good inter-personal and social skills. They will be capable of generating accurate and concise documentation and design notes and be able to disseminate critical information and interact with the design team.