JOB DESCRIPTION:

We are seeking Mixed Signal DV Engineer who will extract modeling specifications from designers and will be involved in development of Analog/Mixed-Signal model in System-Verilog, development of UVM Testbench and developing test cases and run simulation and fix the behavioral model working with Circuit designer. They will also develop timing model for the circuit working with layout engineer.

REQUIRED SKILLS

• AMS Verification, UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools.
• Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc.
• Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,).
• Familiarity with behavioral Verilog code for an analog circuit.
• Ability to write detailed test benches for digital and AMS simulators.
• Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating.
• Familiarity with timing closure and static timing analysis tools.
• Experience with scan chain vector generation and verification.

KEY RESPONSIBILITIES:

• This role will provide the ability to directly influence design related changes as required to meet functional specifications.
• Determine whether anomalous symptoms are caused by errors in the specifications, models, testbench, or design.
• Support integration of composite models into larger composite models maintained by other groups.