Senior Engineer, ASIC Development Engineering at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

29 Jun, 26

Salary

0.0

Posted On

31 Mar, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Asic Verification, System Verilog, Uvm, Verilog, Ip Level Verification, Testbench Architecture Development, Testbench Component Developments, Coverage Closer, Functional Coverage, Gate Level Simulations, Ufs, Pcie, Usb, Mipi, Axi, Python

Industry

Semiconductor Manufacturing

Description

Company Description At Sandisk, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Sandisk is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon. We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future. Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too. We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands. Today’s exceptional challenges require your unique skills. It’s You & Sandisk. Together, we’re the next BIG thing in data. Job Description Experience in ASIC verification, Expertise in System Verilog and UVM, Verilog. · Experience in IP level verification, testbench architecture development, Testbench component developments. Expertise in coverage closer, code coverage, functional coverage Experience in Gate level simulations. · The candidate should be able to define verification plan, create testbenches, testcases,gate level simulations etc independently. · Knowledge on serial protocols UFS, PCIe, USB, MIPI or any other serial protocol. Knowledge on memory protocols - AXI, PCIE, UFS and Flash etc. · Knowledge on scripting languages like Python, Perl etc. · Keen on continuous process improvement to improve Quality and time Qualifications Bachelor of Engineering 2-5 years of experience Additional Information Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

The candidate will be responsible for defining the verification plan, creating testbenches, developing test cases, and executing gate-level simulations independently. This role requires expertise in ASIC verification methodologies and serial/memory protocols.