Senior Engineer, CAD at Micron Technology

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

11 Aug, 26

Salary

0.0

Posted On

13 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Layout Automation, Physical Verification, EDA Tools, Cadence Virtuoso, Synopsys Custom Compiler, AI-Driven Automation, Skill Programming, Python, Perl, Tcl, Linux, CMOS Process, PDN Analysis, DRC/LVS/ERC, Floorplanning, Parasitic Estimation

Industry

Semiconductor Manufacturing

Description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. CAD Engineer Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we create helps make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. Job Description: As a CAD Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities and Tasks include, but not limited to: Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Develop methodologies for highly reliable layout with faster Time to Market approach. Lead layout flows implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization. Continuously evaluate and implement new tools and technologies to improve the current layout development flows. Provide guidance and mentorship to junior members of the team. Develop and deploy AI‑enabled methodologies for Semi-automated floorplanning, parasitic estimation, Qualifications: 5+ years of experience in Layout automation, Physical Verification, or related domains. Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity. Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc. Working experience in PDN analysis tools like Totem/VoltusXFA/XA is preferable. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus. Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up. Good understanding of programming fundamentals, as well as exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proven expertise in defining, developing, and scaling AI‑driven automation and AI‑assisted methodologies for complex layout workflows. Proficiency in working effectively with global teams and stakeholders. Education: A bachelor’s or a master’s degree in Electronics, Electrical or Computer Engineering. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Responsibilities

The role involves evaluating and improving EDA tools and flows for the physical layout and verification of CMOS integrated circuits. You will develop AI-assisted automated workflows and methodologies to increase layout productivity and reduce time to market.