Senior Engineer, Design Verification at Samsung Semiconductor
San Jose, California, USA -
Full Time


Start Date

Immediate

Expiry Date

27 Jun, 25

Salary

243000.0

Posted On

28 Mar, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Good communication skills

Industry

Information Technology/IT

Description

PLEASE NOTE:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

WHAT YOU BRING

  • Bachelor in Electrical, Computer Science or related with 10+ years of experience or Master in Electrical, Computer Science, or related Science with 8+ years of Industry Experience or PhD in Electrical, Computer Science, or related Science with 5+ years of Industry Experience Preferred.
  • Experience in UVM
  • Strong language skills including C++, SystemVerilog
  • Experience in logic and SoC verification from planning to closure
  • Good understanding of verification flows and tools
  • Experience and/or knowledge of the emerging technologies (CXL, Computation in memory and storage, AI LLM accelerators, etc.) in server memory and storage systems
  • Highly motivated with good verbal and written communication skills
  • Creativity in problem-solving
  • You’re inclusive, adapting your style to our people’s situation and diverse global norms.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You’re collaborative, building relationships, humbly offering support, and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

    LI-VL1

Responsibilities
  • Participate in verification strategy and methodology definitions
  • Write Test plans, and participate on test plan definitions
  • Responsible for the verification of modules/subsystems of design Modules
  • Architect test benches, create test plans, implement test bench components in UVM
  • Execute the verification per plan to the closure
  • Work closely with architects and design engineers to define verification requirements, and to close functional and code coverage targets.
  • Work on constraints creation using SVA for functional Coverage
  • Provide support in post silicon bring up and debug
  • Complete other responsibilities as assigned.
    Location: Onsite at our San Jose office/headquarters 5 days a week
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