Your tasks

Analysis of device and system requirements for the optimal selection of system partitioning, architectures, and components.
Development, verification and commissioning of highly complex SoC-FPGAs for DSP or high-bit-rate network applications
Active support of the HW/SW codesign approach in close collaboration with interdisciplinary teams
Agile verification using evaluation boards in conjunction with software development
Performing measurements and validating the components using modern measuring technology
Creation of documentation in accordance with demanding industry standards, especially aerospace requirements.
Participation in the continuous improvement of development processes and methods

Your profile

Successfully completed studies in electrical engineering, communications engineering, computer science or a comparable field
Solid knowledge of VHDL and Verilog , as well as experience with Python and Tcl
Practical experience with Xilinx SoC devices (Zynq or Versal) and the development tools Vivado and Vitis
Experience in programming processors on SoC devices and in handling high-bitrate interfaces
Knowledge of measurement technology for the validation and characterization of components
High level of initiative, sense of responsibility, and strong communication and teamwork skills
Fluent German and English skills, both spoken and written.

Here's what you can expect:

Design of system architectures and concepts for communication systems
Integration of SoCs , FPGAs and peripherals into functional PoC systems
Development and optimization of end-to-end prototypes using internal and external solutions
Conducting system tests as well as analyzing and improving overall performance
Creation of architectural documentation and reusable reference designs

Job requirements

Certain professional and personal qualifications are helpful for this position. The following requirements provide an overview of the experiences and qualities that are advantageous for this role.

What you should bring:

Completed studies in electrical engineering , computer engineering or embedded systems
Several years of experience in system development for communication devices such as satellite or 5G systems
Knowledge of C/C++ , Python , and Linux or RTOS
Experience with HW/SW co-design , SoCs and FPGAs , as well as SDK integrations
Familiarity with communication protocols such as Ethernet, 5G or 6G
Strong problem-solving skills and experience in agile development environments
Excellent English skills and basic German skills

Job Description

In our Munich development center, we design the next generation of ASICs driving leading-edge consumer applications worldwide. As part of our team, you will be at the heart of innovation, shaping the technology of tomorrow.

We are seeking a highly skilled and motivated Digital Design Expert to take responsibility for the digital design of our advanced Mixed-Signal and System-on-Chip (SoC) ASICs.

Help shape the future: You will work on leading edge development projects for MEMS consumer sensor integrated circuits
Use your creativity and freedom: You will work on digital module-level concept definition, requirement derivation, mixed-signal architectural integration
Integrated implementation: You design digital circuits with a focus on optimization regarding area and power
Reliable implementation: You will be responsible for the robust design of digital circuits in control and datapath structures
Structured evaluation: You support the product characterization and validation

Job Description

Are you ready to shape the future of modern mobility systems by taking ownership of digital ASIC design? As a Senior ASIC Digital Lead, you take technical responsibility for the digital design scope across complex ASIC projects. You ensure a consistent and high-quality implementation from specification to integration, actively contributing to the design while driving alignment across all stakeholders and supporting robust DFT and test strategies.

In this position, you take technical responsibility for the digital design scope in ASIC projects, coordinating specification, development, and integration across all stakeholders. You align requirements, structure execution, and drive key technical decisions to ensure a robust and consistent digital implementation.
You act as the central coordination point for all digital design activities, while also contributing hands-on to implementation, ensuring practical feasibility and high-quality results.
Based on system requirements and project objectives, you derive, consolidate, and implement the digital design concept, ensuring consistency across all development phases.
You ensure that DFT and ATPG aspects are properly integrated into the design within the project, planning and aligning activities and ensuring the achievement of defined coverage targets.
Last but not least, you take project-spanning responsibility for the ATPG/DFT flow, ensuring its stable operation, continuous improvement, and consistent application across projects. By analyzing test patterns, silicon data, and defect signatures, you identify root causes and drive targeted improvements in design, test quality, and methodologies. You further enhance efficiency and standardization by developing automation solutions and integrating new tools and methods.

Qualifications

Education: completed university studies in Electrical Engineering, Computer Science or a comparable subject
Experience and Knowledge: several years of experience in digital ASIC development, including top-level integration; proven experience as Digital Lead in project environments; strong expertise in ATPG, test methodologies, coverage analysis, and ATPG tools, including methodology and flow development in digital and ATPG domains; experience in failure analysis using pattern and silicon data; solid understanding of digital verification and interface validation; strong scripting skills (Python, Tcl, or shell); experience in coordinating external development partners and cross-functional teams
Personality and Working Practice: you approach tasks in a structured, responsible, and goal-oriented manner; you possess strong coordination and communication skills, enabling you to effectively drive technical topics across organizational boundaries
Work Routine: while we embrace a hybrid working model, we primarily collaborate on site to foster close teamwork and direct exchange; depending on project requirements and day-to-day responsibilities, the level of on-site presence will be aligned
Languages: fluent in written and spoken English; German is an advantage

Your role

Key responsibilities in your new role

Hands-on digital IP design execution, RTL implementation, design documentation, integration support, and release readiness.
Develop high-quality RTL in System Verilog/Verilog for reusable, configurable, and integration-ready IP blocks.
Drive design quality closure through Lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related sign-off activities.
Debug and resolve block-level, integration-level, and system-level design issues in close collaboration with Verification and Architecture.
Support development and integration of communication and peripheral IPs such as I2C, UART, SPI, AHB/APB-based interfaces, and similar digital IP blocks.
Work with automated, configurable, and generator-based RTL development flows to improve reuse, scalability, consistency, and design productivity.
Establish and follow robust design processes, quality gates, and release practices to minimize bug escapes from the IP qualification flow.
This position is limited to 21 months

Responsibilities