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Senior Engineer Digital Verification (f/m/div) at Infineon Technologies AG Australia

, , Bulgaria -

Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

14 Nov, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Verification, Verification Plans, Verification Methods, Verification Environments, Universal Verification Methodology, System Verilog, Constrained Random Approach, Assertions, Formal Verification, Microcontroller-based ICs, Security Requirements, Safety Requirements, Firmware Design, RTL Design, Verification IPs

Industry

Semiconductor Manufacturing

Description

Create and define verification plans, and be responsible for our verification methods Develop verification environments for our ICs using Universal Verification Methodology (UVM) Draw on test scenarios using System Verilog Verify functionality using the Constrained Random approach Develop assertions in System Verilog for formal verification Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies Provide proactive support to users of our verification flow environment A university degree in Electrical Engineering, Computer Science or a similar academic discipline At least 3 years of experience in Constrained-Random Metric Driven Verification Experience working with microcontroller-based ICs, as well as security and safety requirements Good know-how with UVM, especially using System Verilog Knowledge of firmware and RTL design (VHDL) knowledge of Verification IPs (VIPs) Fluency in English We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

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Responsibilities

Create and define verification plans and develop verification environments for ICs using UVM. Interact with other disciplines to define verification strategies and provide support to users of the verification flow environment.