Senior Engineer – HIG PSE IE for Wafer Reliability Operation at Micron Technology

Taichung, , Taiwan -

Full Time

Start Date

Immediate

Expiry Date

11 Apr, 26

Salary

0.0

Posted On

12 Jan, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Engineering, Semiconductor Reliability, Process Engineering, Project Management, Equipment Planning, Communication, Stakeholder Management, Tactical Planning, Inventory Management, MAM Systems, MES Systems, Capacity Planning, Resource Planning, Cross-Functional Collaboration, Debug System Setup, Quality Assurance

Industry

Semiconductor Manufacturing

Description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a HIG PSE IE for Wafer Reliability Ops, you will lead Wafer Reliability Scheduling and drive the weekly triage meetings between Probe Operations and the Site IE Planning team. This role is critical to ensuring seamless coordination across engineering, manufacturing, and planning functions to support timely and efficient wafer reliability testing. Key Responsibilities Weekly Triage Leadership Facilitate and lead weekly triage meetings with Probe Operations and Site IE Planning to align on: Tester availability Probe card readiness Wafer allocation and production planning Turn-Around-Time (TAT) compliance and issue resolution Wafer Reliability Scheduling Develop and maintain wafer loading plans based on forecast and site capacity. Coordinate with flex cap and probe card teams using IE modeling tools. Execute tactical planning for wafer shipments across sites based on multiple lots execution strategies Capacity & Resource Planning Collaborate with NPI, MH, and PE teams to consolidate HBM roadmap requirements. Build and manage capacity loading plans and dashboards for pre-qual NPI execution Monitor tester and probe card activity, ensuring that usage is recorded and MOR capacity is planned effectively for reporting needs. Process & System Coordination Translate engineering requests into executable test flows in MAM/MES systems. Ensure compliance with RAS audits and QA standards. Support debug system setup and operation for ELFR and Rel Ops Cross-Functional Collaboration Liaise with Fab, IE Planning, and Media Health teams to ensure alignment on wafer-level engineering cycles of learning. Drive for lot staging analysis, and sampling plan execution HIG team member should do him/ her best to demonstrate Micron values in his/ her job performance. People: We care about each other Innovation: We develop solutions that shape the world’s future Tenacity: Nothing shales our resolve Collaboration: We work as one team Customer Focus: We win by knowing our customers Requirements: Bachelor's degree in Engineering or related field. 5+ years of experience in semiconductor reliability operations or process engineering. Strong proficiency in MAM/MES systems, project management, and equipment planning. Excellent communication and stakeholder management skills. Experience with tactical planning and inventory management in a lab or manufacturing setting. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact at hrsupport_taiwan@micron.com. Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Responsibilities

The Senior Engineer will lead Wafer Reliability Scheduling and facilitate weekly triage meetings to ensure coordination between Probe Operations and the Site IE Planning team. This role is essential for managing wafer reliability testing and ensuring compliance with operational standards.