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Senior Engineer MSV at Infineon Technologies AG Australia
Bengaluru, karnataka, India -
Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

14 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

SV Testbench Development, UVM Testbench Development, Analog Functional Spec Understanding, Power Management Blocks, Clock Circuits, Data Converters, Loop Analysis, Verilog, Verilog-AMS, SV, UVM, Cadence Xcelium, Spectre, Synopsys XA-VCS, Mentor Eldo ADMS, Perl, Python

Industry

Semiconductor Manufacturing

Description
Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Bachelors with 5+ years or Masters with 4+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus.

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Responsibilities
The role involves developing and modifying SV and UVM testbenches from a mixed signal perspective. The candidate is expected to drive projects and debug independently while maintaining a schedule and result-oriented execution mindset.