Senior Firmware/Software Engineer at Marvell Technology

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

31 Jan, 26

Salary

158000.0

Posted On

02 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Embedded Firmware, C Programming, C++ Programming, Project Management, Architecture Design, Debugging, Customer Support, Python, Git, Jira, Signal Processing, Networking, DSP, RISC-V, Microcontroller, System Testing

Industry

Semiconductor Manufacturing

Description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Optical Digital Signal Processing (ODSP) PHY SW Team works on Marvell's DSP products used in pluggable optical modules. These chips form the backbone of the internet, moving data within data centers, between data centers, between cities, and even continents over high bandwidth optical fibres. Marvell is the market leader in direct-detect optical DSPs, making chips to fit every application and use case from 100G to 1.6T. These products are in every major cloud data center and AI cluster around the world. Even the data used for this job description has traveled through many of Marvell's DSPs to reach your computer, and our products are a key part of the biggest AI clusters that power all the latest generative AI projects. Check out our products https://www.marvell.com/products/pam-dsp.html The SW team owns all the SW components for the chips, including embedded FW, customer SDK, lab scripts, and GUI applications to interface with the chips. This team is a critical part of the product development flow from pre-silicon simulation, post-silicon lab bring-up, to field deployment. We're the go-to group for getting things done, whether in the field or the lab. The software team is looking for a strong candidate with a positive attitude – ready to tackle any challenge. Join us and get the opportunity to make a meaningful impact on the projects we work on while gaining first-hand experience of what it is like to be part of a high-performing SW development team. What You Can Expect The core responsibilities for the SW team include: Embedded FW that runs on our RISC-V-based multi-core MCU, which controls our proprietary DSP data path C SDK provided to customers for interfacing and controlling our product Python-based GUI for in-field debug, status, and control Build, test, and automated regression infrastructure for the above However the SW team is a key enabler for bringing a product to production, and the roll of a Sr Staff Engineer in our team is to ensure the overall success of that product. For each individual, the role can be some combination of project planning and technical development. This is a highly visible position within the larger organization, you will be a key player in the bringup and development of the product through its entire lifetime. In this position you will be: The technical or project lead on a product, driving the whole SW team dedicated to that project (2-8 other developers) through the development process from collecting requirements to volume production Responsible for the overall Architecture, Design, Development, and Testing of embedded C firmware for controlling our extremely complicated DSP HW Taking lead on difficult to debug issues, drive to root causes with HW/Systems teams, and follow up with test/validation/customer support teams to make sure the issue is resolved Working with the cross-functional team to plan SW milestones, develop in sprints, closing tickets, work with multiple test disciplines, squash all the bugs, and roll out features for the product as a whole Distilling complex systems specifications from standards bodies (MSA/OIF/CMIS) or directly from the customer into easy-to-digest internal documentation, definition of requirements, and clear sequence diagrams to aid in development. Traveling to offices worldwide for product development and chip bring-up (~3weeks/yr, California, Italy, Vietnam) Some possible tasks will be: Mentoring a Jr engineer while working on a difficult HW/SW debug together Developing the use cases, architecture, and system diagrams for a complicated new feature, and integrating that feature into the existing FW & Customer SDK to be as seamless as possible Convert computationally heavy floating point matlab algorithms into fixed point firmware state machines, and coming up with simple ways to compare the two to guarantee functional correctness Working with leads in other teams to develop a post-silicon system test plan for a brand new product Using production FW against the DV simulation environment to root cause a complicated sequencing issue only seen in the field Convincing a large group hardware designers to make changes in next generation products to improve field usability What We're Looking For Minimum Requirements: BS/MS degree in CS/EE or related technical field(s) 3+ years of experience in memory constrained embedded C/C++ FW development SW Team Lead or Technical Lead on embedded projects; project management & release planning, architecture design & development, code reviews & testing, through to customer volume production Understanding of embedded SoC, micro-controller architecture (RISC-V architecture a plus), memory-mapped hardware interfaces, GPIOs, ISRs, etc. Excellent verbal and written communication skills in English, and able to collaborate in a large cross functional organization Excellent problem-solving and customer debug skills on real hardware in the lab Experience with using revision control and defect tracking systems (git & Jira or similar) Preferred but not required: Experience with SERDES, IM-DD/Coherent DSP, Ethernet/PCIe PHYs, and/or Optical Module SW Experience with designing/developing/debugging software state machines, transitions, context saving, error handling Experience with mixed-signal (analog+digital) control and monitoring, PID/feedback loop control, etc. Experience with bare-metal, RTOS, device driver, Linux kernel, etc. Familiarity with advanced compiler options and details (clang/gcc preferred) Proficient in C and Python, with knowledge of git, Linux, makefiles, gdb, IDEs, bash, etc. Familiarity with digital verification test flows, FPGA emulation, hardware languages such as Verilog Familiarity with lab equipment such as oscilloscopes, supplies, PNAs, ONTs, etc. Understanding of networking from the OSI model, with emphasis on the PHY up to the data link level Understanding of signal processing: histograms, BER, SNR, sampling phase, Shannon limit, impulse & frequency response, FFT, etc. Expected Base Pay Range (USD) 105,470 - 158,000, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews. Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AP1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Responsibilities

The core responsibilities include developing embedded firmware for RISC-V-based multi-core MCUs and providing a C SDK for customer interfacing. The role also involves project planning and ensuring the overall success of the product through its entire lifecycle.