Start Date
Immediate
Expiry Date
19 May, 26
Salary
0.0
Posted On
18 Feb, 26
Experience
10 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
FPGA Design, System Verilog, VHDL, HDL, Simulation, Static Timing Analysis, Formal Verification, ModelSim, QuestaSim, Digital Logic Verification, Timing Closure, SDR, C/C++, Python, DSP, SoC
Industry
Telecommunications