Senior FPGA Engineer – Relocation to Spain at Oesia Networks S L

Pontevedra, Galicia, Spain -

Full Time

Start Date

Immediate

Expiry Date

01 Aug, 26

Salary

0.0

Posted On

03 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

VHDL, FPGA, Zynq, UltraScale, Vivado, DOORS, UART, SPI, I2C, AXI Bus, Chipscope, XSCT, SDK, Logic circuit design, Embedded development

Industry

Aviation and Aerospace Component Manufacturing

Description

¡At Oesia Group, we are growing! We would like to count on you for our next job offer: We are looking for a Senior FPGA Engineer – Relocation to Spain to join an important Project located in Vigo / Hibryd job modality. What are we looking for? A Senior FPGA Engineer , with at least 8 years of experience. Availability to join a stable project in Vigo - Nigram. Work Model: Hybrid Work Schedule: Monday - Thruesday: 9:00 - 18:00 / Friday: 9:00 - 14:00 Requirements: Degree in Engineering. Knowledge of synthesizable VHDL. Experience with FPGAs: Zynq and UltraScale. Experience with the Vivado design environment. What will your responsibilities be? Requirements Specification and Traceability: Use of tools such as DOORS to manage and track requirements and their verification through tests. Logic Circuit Design and Verification: Development of advanced synthesizable VHDL code. Verification of logic circuits using VHDL testbenches and simulators such as ModelSim. Control Interface Design: Implementation and management of communication interfaces such as UART, SPI, and I2C. Hands-on work with Xilinx FPGAs, specifically Zynq and UltraScale families. Vivado Design Environment: Use of the Vivado toolchain to develop and verify designs. Design and integration of Xilinx IP cores as well as development of custom IP cores. AXI Bus Implementation and Logic Analysis: Implementation of AXI buses and use of Chipscope for integrated logic analysis. Scripting and Embedded Development: Creation of scripts in XSCT and development of standalone applications in SDK. What we offer you? Work in a multinational company recognized as one of the best companies to work for in 2025, according to Actualidad Económica and Forbes. Stable and innovative technological projects for leading national and international clients. Career plan: we offer an attractive professional career based on experience and personal potential within a continuously evolving company with solid growth. Free access to various training platforms, providing you with a wide multidisciplinary catalog. Flexible compensation. An equal, diverse company with great Corporate Social Responsibility. A positive, healthy, and cooperative work environment. Teamwork is the cornerstone of the company's project successes. Have you heard of us? With over 3.800 professionals in 20 corporate offices across Spain, Brussels, Latin America, and Asia, it generates quality employment and helps people grow in technical careers. Grupo Oesía es una multinacional española dedicada a la ingeniería digital e industrial de uso dual, que desarrolla e implementa proyectos en todo el mundo. En Grupo Oesía creemos en la diversidad y en la igualdad de oportunidades como motor de innovación y en la inclusión como base para el crecimiento. Fomentamos un entorno donde todas las personas sin ningún tipo de distinción puedan desarrollar su talento y contribuir a construir un futuro mejor. Tecnobit-Grupo Oesía diseña, desarrolla, fabrica y mantiene productos tecnológicos de vanguardia y sistemas electrónicos de imagen inteligente, comunicaciones tácticas y seguras y centros de simulación, que constituyen un claro ejemplo de transferencia tecnológica. Nuestros centros tecnológicos en Castilla la Mancha, Andalucía, Galicia, Valencia y Madrid son polos de innovación que contribuyen a la soberanía nacional en capacidades clave y a la autonomía estratégica europea.

Responsibilities

The role involves designing and verifying advanced logic circuits using VHDL and managing requirements through tools like DOORS. You will also be responsible for implementing communication interfaces and developing custom IP cores within the Xilinx Vivado environment.