THE BASICS

• This is a full-time position. This posting is for a current vacancy.
• We’re prioritizing candidates based in the Greater Toronto area, and we’ll ask that you come to our Downtown Toronto office 2-3 times per week.
• Work hours can be flexible, but meetings are typically scheduled between 9 am and 5 pm Eastern Standard Time.
• The salary range for this position is $150,000 - 170,000 per year.
• The hiring manager for this position is Patryk Laskowski, Engineering Manager.

IN THIS ROLE, YOU’LL BE EXPECTED TO:

• Own the design and development of FPGA IP cores across the full lifecycle: concept, architecture, implementation, simulation, validation, and deployment.
• Translate system-level requirements into optimized RTL (VHDL/Verilog/SystemVerilog) architectures.
• Collaborate with software and hardware teams to define and refine hardware/software interfaces.
• Implement signal processing, data acquisition, or control logic modules as needed for the product.
• Develop and execute testbenches and verification strategies using simulation tools (e.g., ModelSim, Questa, Vivado).
• Integrate and validate FPGA designs in real hardware platforms, working closely with lab equipment (oscilloscopes, logic analyzers, etc.).
• Perform timing closure and resource optimization across FPGA architectures.
• Identify and resolve design bottlenecks, bugs, or hardware/software interface issues.
• Guide and mentor junior FPGA or digital design engineers.
• Generate design documentation, test plans, and compliance reports for internal and external stakeholders.

YOU MIGHT BE RIGHT FOR THIS ROLE IF YOU HAVE:

• The ability to break down goals into action items, identify the highest risks, and prioritize appropriately.
• Strong proficiency in Verilog, VHDL, or SystemVerilog.
• Deep knowledge of FPGA development tools (Vivado, Quartus, etc.).
• Experience with embedded systems and hardware/software integration.
• A solid understanding of digital design concepts: pipelining, timing analysis, FSMs, clock domain crossing, etc.
• Familiarity with communication protocols (SPI, I2C, UART, PCIe, etc.)
• The ability to consistently communicate blockers, progress, and delays to all relevant colleagues.