Senior Hardware Engineer at Tower Research Capital

Gurgaon, haryana, India -

Full Time

Start Date

Immediate

Expiry Date

07 Jun, 26

Salary

250000.0

Posted On

09 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Low-latency programming, FPGA technology, Hardware acceleration, ASIC development, Verilog, System Verilog, VHDL, Xilinx, Ethernet protocols, PCIe, Traffic shaping, cocotb, UVM, Static timing analysis, Linux environment, Python

Industry

Financial Services

Description

Tower Research Capital is a leading quantitative trading firm founded in 1998. Tower has built its business on a high-performance platform and independent trading teams. We have a 25+ year track record of innovation and a reputation for discovering unique market opportunities. Tower is home to some of the world’s best systematic trading and engineering talent. We empower portfolio managers to build their teams and strategies independently while providing the economies of scale that come from a large, global organization. Engineers thrive at Tower while developing electronic trading infrastructure at a world class level. Our engineers solve challenging problems in the realms of low-latency programming, FPGA technology, hardware acceleration and machine learning. Our ongoing investment in top engineering talent and technology ensures our platform remains unmatched in terms of functionality, scalability and performance. At Tower, every employee plays a role in our success. Our Business Support teams are essential to building and maintaining the platform that powers everything we do — combining market access, data, compute, and research infrastructure with risk management, compliance, and a full suite of business services. Our Business Support teams enable our trading and engineering teams to perform at their best. At Tower, employees will find a stimulating, results-oriented environment where highly intelligent and motivated colleagues inspire each other to reach their greatest potential. Responsibilities Collaborating with software developers across divisions to architect low-latency connections to financial exchanges around the world Building advanced Ethernet-based communication stacks direct from chip to SFP Integrating network stacks to connect to various financial exchanges Creating custom logic to manage a constant inflow of data, which will need to be parsed, processed, and passed to the user space in the most efficient manner possible Working closely with software developers to develop an optimal interface between FPGA hardware and user space software Qualifications A bachelor’s degree in electrical engineering, or equivalent professional experience At least 5 to 10 years of experience with ASIC and/or FPGA development Verilog or System Verilog programming ASIC development via VHDL or Verilog experience will qualify for the position Expert-level knowledge of FPGA products (Xilinx preferred), development tools, and related simulators Experience with Ethernet protocols, PCIe, and/or switching and routing in network equipment, parsing and traffic shaping. Verification skills using cocotb, formal verification and UVM recommended Experience in FPGA design flow including synthesis, place & route, static timing analysis. A strong understanding of network PHY interfacing Integration experience with independent third-party cores Able to design and develop signal processing cores from system and architectural requirements Ability to document design and interface specifications Experience in Linux environment Comfortable with shell scripting and one or more common scripting languages (e.g. Python) Additional Qualifications A demonstrated background in 100Mbps, 1Gbps, 10Gbps and 40Gbps network interfaces (preferred) An understanding of various network hardware techniques, such as store and forward (preferred) Previous work experience at a high-frequency trading firm (preferred) Experience with collaborating in a global team environment across regions and time zones (plus) Writing kernel drivers for FPGA (plus) C or C++ programming experience (plus) A strong background in mathematics (plus) Anticipated New York annual base salary range $175,000 - $250,000, plus eligible for discretionary bonus Benefits Tower’s headquarters are in the historic Equitable Building, right in the heart of NYC’s Financial District and our impact is global, with over a dozen offices around the world. At Tower, we believe work should be both challenging and enjoyable. That is why we foster a culture where smart, driven people thrive – without the egos. Our open concept workplace, casual dress code, and well-stocked kitchens reflect the value we place on a friendly, collaborative environment where everyone is respected, and great ideas win. Our benefits include: Generous paid time off policies Savings plans and other financial wellness tools available in each region Hybrid working opportunities Free breakfast, lunch, and snacks daily In-office wellness experiences and reimbursement for select wellness expenses (e.g., gym, personal training and more) Company-sponsored sports teams and fitness events (JPM Corporate Challenge, Cycle for Survival, Wall Street Rides FAR and more) Volunteer opportunities and charitable giving Social events, happy hours, treats, and celebrations throughout the year Workshops and continuous learning opportunities At Tower, you’ll find a collaborative and welcoming culture, a diverse team and a workplace that values both performance and enjoyment. No unnecessary hierarchy. No ego. Just great people doing great work – together. Tower Research Capital is an equal opportunity employer.

Responsibilities

The role involves collaborating with software developers to architect low-latency connections to global financial exchanges and building advanced Ethernet-based communication stacks directly from the chip to SFP. Responsibilities also include integrating network stacks, creating custom logic for efficient data processing, and developing optimal interfaces between FPGA hardware and user space software.